pta: qcom: pas: lemans: add GP-DSP0/1 bring-up

Add PAS bring-up for the two general-purpose Hexagon DSPs on Lemans
(SA8775P): GP-DSP0 (TURINGGDSP, image id 39) and GP-DSP1 (TURINGGDSP1,
image id 40). This follows the same architecture as the existing
CDSP0/1, LPASS and IRIS subsystems.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Author: ldts

core/arch/arm/plat-qcom/hoya/lemans/target_config.h

@@ -36,6 +36,18 @@
 #define TURING_1_BASE			UL(0x28000000)
 #define TURING_1_SIZE			UL(0x03000000)
 
+/*
+ * GP-DSP0 / GP-DSP1 (TURINGGDSP / TURINGGDSP1) subsystems. Bases mirror the TZ
+ * HWIO layout (TURINGGDSP_{0,1}_TURING_GDSP_BASE in msmhwiobase.h); the window
+ * covers every GP-DSP sub-block the PTA and clock driver touch (GDSP_CC
+ * 0x808000, PUB 0xc00000, PLL 0xc40000, CORE_CC 0xc48000).
+ */
+#define TURING_GDSP_0_BASE		UL(0x20000000)
+#define TURING_GDSP_0_SIZE		UL(0x01000000)
+
+#define TURING_GDSP_1_BASE		UL(0x21000000)
+#define TURING_GDSP_1_SIZE		UL(0x01000000)
+
 /*
  * LPASS / ADSP (QDSP6 v68/v69) subsystem. Base mirrors the TZ HWIO layout
  * (LPASS_BASE in msmhwiobase.h); the window covers every LPASS sub-block the
@@ -58,6 +70,8 @@
 #define PAS_ID_TURING1			30
 #define PAS_ID_QDSP6			1
 #define PAS_ID_IRIS			9
+#define PAS_ID_GPDSP0			39
+#define PAS_ID_GPDSP1			40
 
 /*
  * CDSP (CDSP0 / TURING) content-protection shared channel in the static TZ DDR
@@ -88,4 +102,16 @@
 
 #define RPMH_PDC_NSP_BASE		UL(0x0b2f0000)
 #define RPMH_PDC_NSP_SIZE		UL(0x00002000)
+
+/*
+ * RPMH PDC blocks for the GP-DSP subsystem reset sequence
+ * (Reset_TURINGGDSPProcessor / Reset_TURINGGDSP1Processor). Bases mirror the TZ
+ * HWIO layout (RPMH_PDC_GPDSP{0,1}_*_PDC_REG_BASE = AOSS_BASE 0x0b000000 +
+ * 0x240000 / 0x2d0000).
+ */
+#define RPMH_PDC_GPDSP0_BASE		UL(0x0b240000)
+#define RPMH_PDC_GPDSP0_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_GPDSP1_BASE		UL(0x0b2d0000)
+#define RPMH_PDC_GPDSP1_SIZE		UL(0x00002000)
 #endif /* TARGET_CONFIG_H */

core/drivers/clk/qcom/clock-qcom.c

@@ -161,6 +161,8 @@ TEE_Result qcom_clock_enable(enum qcom_clk_group group)
 	case QCOM_CLKS_TURING1:
 	case QCOM_CLKS_LPASS:
 	case QCOM_CLKS_WPSS:
+	case QCOM_CLKS_GPDSP0:
+	case QCOM_CLKS_GPDSP1:
 		return qcom_clock_enable_pas(group);
 	default:
 		EMSG("Unsupported clock group %d\n", group);

core/drivers/clk/qcom/platform/lemans/clock-qcom-pas.c

@@ -25,6 +25,8 @@ register_phys_mem(MEM_AREA_IO_NSEC, RPMH_PDC_GLOBAL_BASE, RPMH_PDC_GLOBAL_SIZE);
 register_phys_mem(MEM_AREA_IO_NSEC, RPMH_PDC_COMPUTE_BASE,
 		  RPMH_PDC_COMPUTE_SIZE);
 register_phys_mem(MEM_AREA_IO_NSEC, RPMH_PDC_NSP_BASE, RPMH_PDC_NSP_SIZE);
+register_phys_mem(MEM_AREA_IO_NSEC, RPMH_PDC_GPDSP0_BASE, RPMH_PDC_GPDSP0_SIZE);
+register_phys_mem(MEM_AREA_IO_NSEC, RPMH_PDC_GPDSP1_BASE, RPMH_PDC_GPDSP1_SIZE);
 register_phys_mem(MEM_AREA_IO_NSEC, TCSR_MUTEX_BASE, TCSR_MUTEX_SIZE);
 
 static TEE_Result cdsp_enable(paddr_t turing_base)
@@ -183,6 +185,72 @@ static TEE_Result lpass_setup(void)
 				   Q6RCG_CFG_VALUE);
 }
 
+static const struct qcom_lucidevo_pll_config gpdsp_q6_pll_cfg = {
+	.l_val = GPDSP_Q6_PLL_L_VAL,
+	.cal_l_val = GPDSP_Q6_PLL_CAL_L_VAL,
+	.pre_div = 1,
+	.config_ctl = GPDSP_Q6_PLL_CONFIG_CTL,
+	.config_ctl_u = GPDSP_Q6_PLL_CONFIG_CTL_U,
+	.config_ctl_u1 = GPDSP_Q6_PLL_CONFIG_CTL_U1,
+	.user_ctl = GPDSP_Q6_PLL_USER_CTL,
+	.user_ctl_u = GPDSP_Q6_PLL_USER_CTL_U,
+	/* alpha (default) fractional mode */
+};
+
+/*
+ * Set up clocks for a GP-DSP (TURINGGDSP) QDSP6, mirroring
+ * Setup_TURINGGDSPProcessor in the reference ClockPIL driver. Like LPASS (and
+ * unlike the Turing NSP), the Q6 PLL and core RCG are configured here, before
+ * the boot FSM is triggered in gpdspN_fw_start; the core itself is released by
+ * BOOT_CORE_START in fw_start, so there is no separate post-boot step. The
+ * subsystem window is mapped by the PAS PTA mem-setup, so each sub-block base
+ * is resolved via io_pa_or_va against the GP-DSP base + offset.
+ */
+static TEE_Result gpdsp_setup(paddr_t gdsp_base, uint32_t gcc_cfg_ahb_cbcr,
+			      uint32_t gcc_aggre_axi_cbcr)
+{
+	struct io_pa_va gcc_io = { .pa = GCC_BASE };
+	vaddr_t gcc_base = io_pa_or_va(&gcc_io, GCC_SIZE);
+	struct io_pa_va gdsp_io = { .pa = gdsp_base };
+	vaddr_t base = io_pa_or_va(&gdsp_io, TURING_GDSP_0_SIZE);
+	vaddr_t gdsp_cc = base + TURINGGDSP_GDSP_CC_OFFSET;
+	vaddr_t core_cc = base + TURINGGDSP_CORE_CC_OFFSET;
+	vaddr_t pll_base = base + TURINGGDSP_PLL_OFFSET;
+	vaddr_t pub = base + TURINGGDSP_PUB_OFFSET;
+	TEE_Result res = TEE_SUCCESS;
+
+	if (!gcc_base || !base)
+		return TEE_ERROR_GENERIC;
+
+	/* Turing slave-way bus clock branch, also on NIU socket. */
+	res = qcom_clock_enable_cbc(gcc_base + gcc_cfg_ahb_cbcr);
+	if (res != TEE_SUCCESS)
+		return res;
+
+	res = qcom_clock_enable_cbc(gcc_base + gcc_aggre_axi_cbcr);
+	if (res != TEE_SUCCESS)
+		return res;
+
+	/* Q6SS slave clock, required to reach the QDSP6SS registers. */
+	res = qcom_clock_enable_cbc(gdsp_cc + TURINGGDSP_Q6SS_AHBS_AON_CBCR);
+	if (res != TEE_SUCCESS)
+		return res;
+
+	/* Program the debug config register, then enable core clock. */
+	io_write32(pub + TURINGGDSP_QDSP6SS_DBG_CFG, 0);
+	io_setbits32(core_cc + TURINGGDSP_QDSP6SS_CORE_CBCR,
+		     CBCR_BRANCH_ENABLE_BIT);
+
+	/* Configure and lock the Q6 PLL, then switch the core RCG onto it. */
+	res = qcom_lucidevo_pll_enable(pll_base, &gpdsp_q6_pll_cfg);
+	if (res != TEE_SUCCESS)
+		return res;
+
+	return qcom_clock_set_rate(core_cc + TURINGGDSP_QDSP6SS_CORE_CFG_RCGR,
+				   core_cc + TURINGGDSP_QDSP6SS_CORE_CMD_RCGR,
+				   Q6RCG_CFG_VALUE);
+}
+
 TEE_Result qcom_clock_enable_pas_processor(enum qcom_clk_group group)
 {
 	switch (group) {
@@ -199,6 +267,15 @@ TEE_Result qcom_clock_enable_pas_processor(enum qcom_clk_group group)
 		 * there is no separate post-boot step here.
 		 */
 		return TEE_SUCCESS;
+	case QCOM_CLKS_GPDSP0:
+	case QCOM_CLKS_GPDSP1:
+		/*
+		 * Like LPASS, the GP-DSP Q6 PLL and core RCG are configured in
+		 * gpdsp_setup (before the boot FSM); the core is released by
+		 * BOOT_CORE_START in gpdspN_fw_start, so there is no separate
+		 * post-boot step here.
+		 */
+		return TEE_SUCCESS;
 	default:
 		return TEE_ERROR_NOT_SUPPORTED;
 	}
@@ -348,13 +425,150 @@ static TEE_Result cdsp_reset_processor(const struct cdsp_reset_regs *r)
 	return TEE_SUCCESS;
 }
 
+/*
+ * Per-instance register selection for the GP-DSP reset sequence. GDSP0 and
+ * GDSP1 share the QDSP6 PUB offsets (parameterised by gdsp_base) but differ in
+ * the GCC AHB CBCR, the TCSR halt/idle/power block, and the PDC / AOSS restart
+ * fields.
+ */
+struct gpdsp_reset_regs {
+	paddr_t gdsp_base;
+	uint32_t gcc_cfg_ahb_cbcr;	/* offset within GCC window */
+	uint32_t tcsr_haltreq;		/* offsets within TCSR mutex window */
+	uint32_t tcsr_haltack;
+	uint32_t tcsr_il0_master_idle;
+	uint32_t tcsr_il1_master_idle;
+	uint32_t tcsr_pwr_on;
+	paddr_t pdc_status_base;	/* RPMH PDC block for the busy check */
+	uint32_t pdc_status_size;
+	uint32_t pdc_sync_reset_bit;	/* field within RPMH_PDC_SYNC_RESET */
+	uint32_t gpdsp_restart_bit;	/* field within AOSS_CC_GPDSP_RESTART */
+};
+
+static const struct gpdsp_reset_regs gpdsp0_reset_regs = {
+	.gdsp_base = TURING_GDSP_0_BASE,
+	.gcc_cfg_ahb_cbcr = GCC_GPDSP_0_CFG_AHB_CBCR,
+	.tcsr_haltreq = TCSR_GPDSP0_HALT_REQ,
+	.tcsr_haltack = TCSR_GPDSP0_HALT_ACK,
+	.tcsr_il0_master_idle = TCSR_GPDSP0_IL0_MASTER_IDLE,
+	.tcsr_il1_master_idle = TCSR_GPDSP0_IL1_MASTER_IDLE,
+	.tcsr_pwr_on = TCSR_GPDSP0_PWR_ON,
+	.pdc_status_base = RPMH_PDC_GPDSP0_BASE,
+	.pdc_status_size = RPMH_PDC_GPDSP0_SIZE,
+	.pdc_sync_reset_bit = PDC_SYNC_RESET_GPDSP0_BIT,
+	.gpdsp_restart_bit = GPDSP_RESTART_SS_0_BIT,
+};
+
+static const struct gpdsp_reset_regs gpdsp1_reset_regs = {
+	.gdsp_base = TURING_GDSP_1_BASE,
+	.gcc_cfg_ahb_cbcr = GCC_GPDSP_1_CFG_AHB_CBCR,
+	.tcsr_haltreq = TCSR_GPDSP1_HALT_REQ,
+	.tcsr_haltack = TCSR_GPDSP1_HALT_ACK,
+	.tcsr_il0_master_idle = TCSR_GPDSP1_IL0_MASTER_IDLE,
+	.tcsr_il1_master_idle = TCSR_GPDSP1_IL1_MASTER_IDLE,
+	.tcsr_pwr_on = TCSR_GPDSP1_PWR_ON,
+	.pdc_status_base = RPMH_PDC_GPDSP1_BASE,
+	.pdc_status_size = RPMH_PDC_GPDSP1_SIZE,
+	.pdc_sync_reset_bit = PDC_SYNC_RESET_GPDSP1_BIT,
+	.gpdsp_restart_bit = GPDSP_RESTART_SS_1_BIT,
+};
+
+/* HALT_ACK polls for up to 1s (200000 * 5us), matching the reference. */
+#define GPDSP_HALT_ACK_TIMEOUT_US	(200000 * 5)
+
+/*
+ * Put a GP-DSP QDSP6 through a full subsystem reset before bring-up, mirroring
+ * Reset_TURINGGDSPProcessor / Reset_TURINGGDSP1Processor in the reference
+ * ClockPIL. This returns the core to a clean state (asserting
+ * AOSS_CC_GPDSP_RESTART and the PDC sync reset) so the Q6 does not come out of
+ * reset from a stale or partially-initialised state. Unlike the Turing NSP,
+ * there is no NSPAUX/ALT_RESET retention handling and the master-port idle
+ * check covers two ports (IL0 and IL1).
+ */
+static TEE_Result gpdsp_reset_processor(const struct gpdsp_reset_regs *r)
+{
+	struct io_pa_va gdsp_io = { .pa = r->gdsp_base };
+	vaddr_t base = io_pa_or_va(&gdsp_io, TURING_GDSP_0_SIZE);
+	vaddr_t pub = base + TURINGGDSP_PUB_OFFSET;
+	struct io_pa_va gcc_io = { .pa = GCC_BASE };
+	vaddr_t gcc_base = io_pa_or_va(&gcc_io, GCC_SIZE);
+	struct io_pa_va aoss_io = { .pa = AOSS_CC_BASE };
+	vaddr_t aoss_cc = io_pa_or_va(&aoss_io, AOSS_CC_SIZE);
+	struct io_pa_va pdc_g_io = { .pa = RPMH_PDC_GLOBAL_BASE };
+	vaddr_t pdc_global = io_pa_or_va(&pdc_g_io, RPMH_PDC_GLOBAL_SIZE);
+	struct io_pa_va pdc_s_io = { .pa = r->pdc_status_base };
+	vaddr_t pdc_status = io_pa_or_va(&pdc_s_io, r->pdc_status_size);
+	struct io_pa_va tcsr_io = { .pa = TCSR_MUTEX_BASE };
+	vaddr_t tcsr = io_pa_or_va(&tcsr_io, TCSR_MUTEX_SIZE);
+	uint64_t timeout = 0;
+
+	if (!base || !gcc_base || !aoss_cc || !pdc_global || !pdc_status ||
+	    !tcsr)
+		return TEE_ERROR_GENERIC;
+
+	/* Bail if the PDC sequencer is mid-transition. */
+	if (io_read32(pdc_status + RPMH_PDC_MODE_STATUS_DRV0) &
+	    PDC_MODE_STATUS_SEQ_BUSY_BIT)
+		return TEE_ERROR_BUSY;
+
+	/* Reset the retention logic and let the write settle. */
+	io_setbits32(pub + TURINGGDSP_QDSP6SS_RET_CFG,
+		     QDSP6SS_RET_CFG_RET_ARES_ENA_BIT);
+	dsb();
+	udelay(2000);
+
+	/* Disconnect the SWAY NIU socket to halt config-NoC traffic. */
+	io_clrbits32(gcc_base + r->gcc_cfg_ahb_cbcr, CBCR_CLK_ENABLE_BIT);
+
+	/*
+	 * If powered on and either master port (IL0 or IL1) is busy, halt
+	 * mem-NoC traffic and wait for the acknowledge.
+	 */
+	if (io_read32(tcsr + r->tcsr_pwr_on) & TCSR_TURING_BIT) {
+		if (!(io_read32(tcsr + r->tcsr_il0_master_idle) &
+		      TCSR_TURING_BIT) ||
+		    !(io_read32(tcsr + r->tcsr_il1_master_idle) &
+		      TCSR_TURING_BIT)) {
+			io_setbits32(tcsr + r->tcsr_haltreq, TCSR_TURING_BIT);
+
+			timeout = timeout_init_us(GPDSP_HALT_ACK_TIMEOUT_US);
+			while (!(io_read32(tcsr + r->tcsr_haltack) &
+				 TCSR_TURING_BIT)) {
+				if (timeout_elapsed(timeout))
+					break;
+				udelay(5);
+			}
+		}
+	}
+
+	/* Assert the PDC reset, then pulse the subsystem restart. */
+	io_setbits32(pdc_global + RPMH_PDC_SYNC_RESET, r->pdc_sync_reset_bit);
+
+	io_setbits32(aoss_cc + AOSS_CC_GPDSP_RESTART, r->gpdsp_restart_bit);
+	udelay(200);
+	io_clrbits32(aoss_cc + AOSS_CC_GPDSP_RESTART, r->gpdsp_restart_bit);
+	dsb();
+	udelay(200);
+
+	/* De-assert the PDC reset and clear the halt request. */
+	io_clrbits32(pdc_global + RPMH_PDC_SYNC_RESET, r->pdc_sync_reset_bit);
+	io_clrbits32(tcsr + r->tcsr_haltreq, TCSR_TURING_BIT);
+	udelay(100);
+
+	return TEE_SUCCESS;
+}
+
 TEE_Result qcom_clock_pas_reset(enum qcom_clk_group group)
 {
 	switch (group) {
 	case QCOM_CLKS_TURING:
 		return cdsp_reset_processor(&cdsp0_reset_regs);
 	case QCOM_CLKS_TURING1:
 		return cdsp_reset_processor(&cdsp1_reset_regs);
+	case QCOM_CLKS_GPDSP0:
+		return gpdsp_reset_processor(&gpdsp0_reset_regs);
+	case QCOM_CLKS_GPDSP1:
+		return gpdsp_reset_processor(&gpdsp1_reset_regs);
 	case QCOM_CLKS_LPASS:
 		/*
 		 * The LPASS subsystem reset (Reset_LPASSProcessor) is
@@ -399,6 +613,12 @@ TEE_Result qcom_clock_enable_pas(enum qcom_clk_group group)
 		break;
 	case QCOM_CLKS_LPASS:
 		return lpass_setup();
+	case QCOM_CLKS_GPDSP0:
+		return gpdsp_setup(TURING_GDSP_0_BASE, GCC_GPDSP_0_CFG_AHB_CBCR,
+				   GCC_AGGRE_NOC_GPDSP_0_AXI_CBCR);
+	case QCOM_CLKS_GPDSP1:
+		return gpdsp_setup(TURING_GDSP_1_BASE, GCC_GPDSP_1_CFG_AHB_CBCR,
+				   GCC_AGGRE_NOC_GPDSP_1_AXI_CBCR);
 	default:
 		return TEE_ERROR_NOT_SUPPORTED;
 	}

core/drivers/clk/qcom/platform/lemans/clock_group_qcom.h

@@ -163,4 +163,77 @@
 #define LPASS_Q6_PLL_USER_CTL			0x00000000
 #define LPASS_Q6_PLL_USER_CTL_U			0x00400805
 
+/*
+ * GP-DSP0 / GP-DSP1 (TURINGGDSP / TURINGGDSP1, QDSP6 v68/v69). All sub-block
+ * offsets are relative to TURING_GDSP_{0,1}_BASE; the subsystem window is
+ * mapped once by the PAS PTA (pas_platform_mem_setup) and by the clock driver,
+ * so each sub-block base is derived as TURING_GDSP_n_BASE + offset. The two
+ * instances share these offsets; only the subsystem base differs.
+ */
+#define TURINGGDSP_GDSP_CC_OFFSET		0x00808000
+#define TURINGGDSP_PUB_OFFSET			0x00c00000
+#define TURINGGDSP_PLL_OFFSET			0x00c40000
+#define TURINGGDSP_CORE_CC_OFFSET		0x00c48000
+
+/* Offsets within the GDSP_CC block (TURINGGDSP_GDSP_CC_OFFSET). */
+#define TURINGGDSP_Q6SS_AHBS_AON_CBCR		0x10
+
+/* Offsets within the QDSP6 PUB block (TURINGGDSP_PUB_OFFSET). */
+#define TURINGGDSP_QDSP6SS_RST_EVB		0x10
+#define TURINGGDSP_QDSP6SS_DBG_CFG		0x18
+#define TURINGGDSP_QDSP6SS_RET_CFG		0x1c
+#define TURINGGDSP_QDSP6SS_BOOT_CORE_START	0x400
+#define TURINGGDSP_QDSP6SS_BOOT_CMD		0x404
+#define TURINGGDSP_QDSP6SS_BOOT_STATUS		0x408
+
+/* Offsets in the core clock-controller block (TURINGGDSP_CORE_CC_OFFSET). */
+#define TURINGGDSP_QDSP6SS_CORE_CMD_RCGR	0x0
+#define TURINGGDSP_QDSP6SS_CORE_CFG_RCGR	0x4
+#define TURINGGDSP_QDSP6SS_CORE_CBCR		0x20
+
+/* GCC config-NoC AHB / aggre-NoC AXI branches (within GCC window). */
+#define GCC_GPDSP_0_CFG_AHB_CBCR		0x16008
+#define GCC_AGGRE_NOC_GPDSP_0_AXI_CBCR		0x16004
+#define GCC_GPDSP_1_CFG_AHB_CBCR		0x15008
+#define GCC_AGGRE_NOC_GPDSP_1_AXI_CBCR		0x15004
+
+/* AOSS_CC GP-DSP subsystem restart (within AOSS_CC window). */
+#define AOSS_CC_GPDSP_RESTART			0x4f034
+#define GPDSP_RESTART_SS_0_BIT			BIT(0)
+#define GPDSP_RESTART_SS_1_BIT			BIT(1)
+
+/* RPMH PDC global sync-reset bits for GP-DSP (in RPMH_PDC_GLOBAL window). */
+#define PDC_SYNC_RESET_GPDSP0_BIT		BIT(1)
+#define PDC_SYNC_RESET_GPDSP1_BIT		BIT(10)
+
+/*
+ * TCSR GP-DSP master-halt / power registers (offsets within the TCSR mutex
+ * window). The GDSP1 block sits 0x14 above the GDSP0 block. Unlike the Turing
+ * NSP, the reset sequence checks two master-idle bits (IL0 and IL1).
+ */
+#define TCSR_GPDSP0_HALT_REQ			0x32000
+#define TCSR_GPDSP0_HALT_ACK			0x32004
+#define TCSR_GPDSP0_IL0_MASTER_IDLE		0x32008
+#define TCSR_GPDSP0_IL1_MASTER_IDLE		0x3200c
+#define TCSR_GPDSP0_PWR_ON			0x32010
+#define TCSR_GPDSP1_HALT_REQ			0x32014
+#define TCSR_GPDSP1_HALT_ACK			0x32018
+#define TCSR_GPDSP1_IL0_MASTER_IDLE		0x3201c
+#define TCSR_GPDSP1_IL1_MASTER_IDLE		0x32020
+#define TCSR_GPDSP1_PWR_ON			0x32024
+
+/*
+ * GP-DSP Q6 Lucid-EVO PLL settings, taken from the reference clock driver
+ * HALclkPLLSettings.h (HAL_CLK_TURING_GDSP_CC_{0,1}_QDSP6SS_CORE_CC_PLL_*).
+ * Identical for both instances; differs from the Turing NSP Q6 PLL only in the
+ * L value.
+ */
+#define GPDSP_Q6_PLL_L_VAL			0x3A
+#define GPDSP_Q6_PLL_CAL_L_VAL			0x44
+#define GPDSP_Q6_PLL_CONFIG_CTL			0x20485699
+#define GPDSP_Q6_PLL_CONFIG_CTL_U		0x00182261
+#define GPDSP_Q6_PLL_CONFIG_CTL_U1		0x32AA299C
+#define GPDSP_Q6_PLL_USER_CTL			0x00000000
+#define GPDSP_Q6_PLL_USER_CTL_U			0x00400805
+
 #endif /* _CLOCK_GROUP_QCOM_H_ */