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Pierrick Bouvier
committed
Revert "WIP: single-binary cpu arm"
This reverts commit 02dbe9e. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
1 parent 2531de8 commit 6732a9e

9 files changed

Lines changed: 18 additions & 62 deletions

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‎hw/core/cpu-common.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -429,7 +429,7 @@ void list_cpus(void)
429429
} else {
430430
GSList *list;
431431

432-
list = get_cpu_types_available();
432+
list = object_class_get_list_sorted(TYPE_CPU, false);
433433
qemu_printf("Available CPUs:\n");
434434
g_slist_foreach(list, cpu_list_entry, NULL);
435435
g_slist_free(list);

‎include/qemu/target-info-qom.h‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -50,13 +50,6 @@ void target_info_qom_set_target_from_argv0(const char *argv0);
5050
*/
5151
GSList *machine_get_types_available(void);
5252

53-
/**
54-
* get_cpu_types_available:
55-
*
56-
* Returns: Cpu classes available for the selected target.
57-
*/
58-
GSList *get_cpu_types_available(void);
59-
6053
extern const InterfaceInfo type_target_specific[];
6154

6255
#endif /* QEMU_TARGET_INFO_QOM_H */

‎target-info-qom.c‎

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -61,13 +61,6 @@ GSList *machine_get_types_available(void)
6161
return filter_types_available(machines);
6262
}
6363

64-
GSList *get_cpu_types_available(void)
65-
{
66-
GSList *cpu = object_class_get_list_sorted(TYPE_CPU, false);
67-
68-
return filter_types_available(cpu);
69-
}
70-
7164
static void target_info_qom_class_init(ObjectClass *oc, const void * data)
7265
{
7366
TargetInfoQomClass *klass = TARGET_INFO_CLASS(oc);

‎target/arm/cpu.c‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2668,9 +2668,6 @@ static void cpu_register_class_init(ObjectClass *oc, const void *data)
26682668
if (acc->info->deprecation_note) {
26692669
cc->deprecation_note = acc->info->deprecation_note;
26702670
}
2671-
if (acc->info->is_available) {
2672-
TARGET_SPECIFIC_CLASS(oc)->is_available = acc->info->is_available;
2673-
}
26742671
}
26752672

26762673
void arm_cpu_register(const ARMCPUInfo *info)
@@ -2681,9 +2678,6 @@ void arm_cpu_register(const ARMCPUInfo *info)
26812678
.class_init = info->class_init ?: cpu_register_class_init,
26822679
.class_data = info,
26832680
};
2684-
if (info->is_available) {
2685-
type_info.interfaces = type_target_specific;
2686-
}
26872681

26882682
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
26892683
type_register_static(&type_info);

‎target/arm/cpu.h‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1178,7 +1178,6 @@ typedef struct ARMCPUInfo {
11781178
const char *deprecation_note;
11791179
void (*initfn)(Object *obj);
11801180
void (*class_init)(ObjectClass *oc, const void *data);
1181-
bool (*is_available)(void);
11821181
} ARMCPUInfo;
11831182

11841183
/**

‎target/arm/cpu64.c‎

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -822,13 +822,10 @@ void aarch64_host_initfn(Object *obj)
822822
}
823823

824824
static const ARMCPUInfo aarch64_cpus[] = {
825-
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn,
826-
.is_available = target_aarch64 },
827-
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn,
828-
.is_available = target_aarch64 },
825+
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
826+
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
829827
#if defined(CONFIG_KVM) || defined(CONFIG_HVF) || defined(CONFIG_WHPX)
830-
{ .name = "host", .initfn = aarch64_host_initfn,
831-
.is_available = target_aarch64 },
828+
{ .name = "host", .initfn = aarch64_host_initfn },
832829
#endif
833830
};
834831

‎target/arm/tcg/cpu32.c‎

Lines changed: 3 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020

2121

2222
/* CPU models. These are not needed for the AArch64 linux-user build. */
23-
#if !defined(CONFIG_USER_ONLY)
23+
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
2424

2525
static void arm926_initfn(Object *obj)
2626
{
@@ -711,18 +711,8 @@ static void sa1110_initfn(Object *obj)
711711
cpu->reset_sctlr = 0x00000070;
712712
}
713713

714-
static bool arm_cpu32_is_available(void)
715-
{
716-
#ifdef CONFIG_USER_ONLY
717-
return target_arm();
718-
#else
719-
return target_base_arm();
720-
#endif
721-
}
722-
723714
static const ARMCPUInfo arm_tcg_cpus[] = {
724-
{ .name = "arm926", .initfn = arm926_initfn,
725-
.is_available = arm_cpu32_is_available },
715+
{ .name = "arm926", .initfn = arm926_initfn },
726716
{ .name = "arm946", .initfn = arm946_initfn },
727717
{ .name = "arm1026", .initfn = arm1026_initfn },
728718
/*
@@ -757,4 +747,4 @@ static void arm_tcg_cpu_register_types(void)
757747

758748
type_init(arm_tcg_cpu_register_types)
759749

760-
#endif /* !CONFIG_USER_ONLY */
750+
#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */

‎target/arm/tcg/cpu64.c‎

Lines changed: 10 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1446,30 +1446,20 @@ void aarch64_max_tcg_initfn(Object *obj)
14461446
}
14471447

14481448
static const ARMCPUInfo aarch64_cpus[] = {
1449-
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn,
1450-
.is_available = target_aarch64 },
1451-
{ .name = "cortex-a55", .initfn = aarch64_a55_initfn,
1452-
.is_available = target_aarch64 },
1453-
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn,
1454-
.is_available = target_aarch64 },
1455-
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn,
1456-
.is_available = target_aarch64 },
1449+
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
1450+
{ .name = "cortex-a55", .initfn = aarch64_a55_initfn },
1451+
{ .name = "cortex-a72", .initfn = aarch64_a72_initfn },
1452+
{ .name = "cortex-a76", .initfn = aarch64_a76_initfn },
14571453
/*
14581454
* The Cortex-A78AE differs slightly from the plain Cortex-A78. We don't
14591455
* currently model the latter.
14601456
*/
1461-
{ .name = "cortex-a78ae", .initfn = aarch64_a78ae_initfn,
1462-
.is_available = target_aarch64 },
1463-
{ .name = "cortex-a710", .initfn = aarch64_a710_initfn,
1464-
.is_available = target_aarch64 },
1465-
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn,
1466-
.is_available = target_aarch64 },
1467-
{ .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn,
1468-
.is_available = target_aarch64 },
1469-
{ .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn,
1470-
.is_available = target_aarch64 },
1471-
{ .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn,
1472-
.is_available = target_aarch64 },
1457+
{ .name = "cortex-a78ae", .initfn = aarch64_a78ae_initfn },
1458+
{ .name = "cortex-a710", .initfn = aarch64_a710_initfn },
1459+
{ .name = "a64fx", .initfn = aarch64_a64fx_initfn },
1460+
{ .name = "neoverse-n1", .initfn = aarch64_neoverse_n1_initfn },
1461+
{ .name = "neoverse-v1", .initfn = aarch64_neoverse_v1_initfn },
1462+
{ .name = "neoverse-n2", .initfn = aarch64_neoverse_n2_initfn },
14731463
};
14741464

14751465
static void aarch64_cpu_register_types(void)

‎target/arm/tcg/meson.build‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ translate32_d = [
3030
arm_ss.add(when: 'TARGET_AARCH64', if_true: gen_a64)
3131
arm_stubs_ss.add(files('stubs32.c'))
3232

33-
arm_common_user_system_ss.add(files(
33+
arm_ss.add(files(
3434
'cpu32.c',
3535
))
3636

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