From 65436aab1d158f614ceb164816cd8d64001d238f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pawe=C5=82=20P=C5=82=C3=B3ciennik?= Date: Sun, 23 Apr 2023 12:20:50 +0200 Subject: [PATCH] spi in_base pin_sck to pin_miso. --- pio/pio_spi.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pio/pio_spi.py b/pio/pio_spi.py index 30f02c3..cfdc697 100644 --- a/pio/pio_spi.py +++ b/pio/pio_spi.py @@ -27,7 +27,7 @@ class PIOSPI: def __init__(self, sm_id, pin_mosi, pin_miso, pin_sck, cpha=False, cpol=False, freq=1000000): assert(not(cpol or cpha)) - self._sm = rp2.StateMachine(sm_id, spi_cpha0, freq=4*freq, sideset_base=Pin(pin_sck), out_base=Pin(pin_mosi), in_base=Pin(pin_sck)) + self._sm = rp2.StateMachine(sm_id, spi_cpha0, freq=4*freq, sideset_base=Pin(pin_sck), out_base=Pin(pin_mosi), in_base=Pin(pin_miso)) self._sm.active(1) # Note this code will die spectacularly cause we're not draining the RX FIFO