irq

Author: ZR233

axplat/src/time.rs

@@ -41,6 +41,9 @@ pub trait TimeIf {
     /// deadline (in nanoseconds).
     #[cfg(feature = "irq")]
     fn set_oneshot_timer(deadline_ns: u64);
+
+    #[cfg(feature = "irq")]
+    fn irq_num()->usize;
 }
 
 /// Returns nanoseconds elapsed since system boot.

platforms/axplat-aarch64-dyn/Cargo.toml

@@ -10,20 +10,22 @@ version = "0.1.0"
 
 [features]
 fp-simd = ["axcpu/fp-simd"]
+hv = []
+irq = ["axplat/irq"]
 smp = ["axplat/smp"]
 
 [dependencies]
 aarch64-cpu = "10"
 any-uart = "0.2.11"
 axconfig-macros = "0.2"
 axcpu = {workspace = true}
-axplat = {workspace = true, features = ["irq"]}
+axplat = {workspace = true}
 fdt-parser = "0.4"
 heapless = "0.8"
+lazyinit = "0.2"
 log = "0.4"
 memory_addr = "0.3"
 pie-boot = {version = "0.2.9"}
 rdrive = "0.15"
 smccc = "0.2"
 spin = "0.10"
-lazyinit = "0.2"

platforms/axplat-aarch64-dyn/src/init.rs

@@ -70,15 +70,23 @@ impl InitIf for InitIfImpl {
     /// * Other platform devices are initialized.
     fn init_later(cpu_id: usize, arg: usize) {
         driver::setup();
-        crate::irq::init();
-        crate::irq::init_current_cpu();
+        #[cfg(feature = "irq")]
+        {
+            crate::irq::init();
+            crate::irq::init_current_cpu();
+            crate::time::enable_irqs();
+        }
     }
 
     /// Initializes the platform at the later stage for secondary cores.
     ///
     /// See [`init_later`] for details.
     #[cfg(feature = "smp")]
     fn init_later_secondary(cpu_id: usize) {
-        crate::irq::init_current_cpu();
+        #[cfg(feature = "irq")]
+        {
+            crate::irq::init_current_cpu();
+            crate::time::enable_irqs();
+        }
     }
 }

platforms/axplat-aarch64-dyn/src/irq.rs

@@ -1,4 +1,6 @@
 use aarch64_cpu::registers::*;
+use alloc::{format, string::String};
+
 use axplat::irq::{HandlerTable, IrqHandler, IrqIf};
 use lazyinit::LazyInit;
 use log::{debug, trace, warn};
@@ -22,30 +24,7 @@ struct IrqIfImpl;
 impl IrqIf for IrqIfImpl {
     /// Enables or disables the given IRQ.
     fn set_enable(irq_raw: usize, enabled: bool) {
-        trace!("IRQ set enable: {:#x} {}", irq_raw, enabled);
-        let irq: IrqId = irq_raw.into();
-        if is_irq_private(irq_raw)
-            && let local::Capability::ConfigLocalIrq(c) = CPU_IF.capability()
-        {
-            if enabled {
-                c.irq_enable(irq).expect("failed to enable local IRQ");
-            } else {
-                c.irq_disable(irq).expect("failed to disable local IRQ");
-            }
-        } else {
-            let mut intc = get_gicd().lock().unwrap();
-            if enabled {
-                intc.irq_enable(irq).expect("failed to enable IRQ");
-            } else {
-                intc.irq_disable(irq).expect("failed to disable IRQ");
-            }
-
-            if !is_irq_private(irq_raw) {
-                // For private IRQs, we need to acknowledge the interrupt
-                // controller.
-                intc.set_target_cpu(irq, current_cpu().into());
-            }
-        }
+        set_enable(irq_raw, is_irq_private(irq_raw), None, enabled);
     }
 
     /// Registers an IRQ handler for the given IRQ.
@@ -96,13 +75,15 @@ impl IrqIf for IrqIfImpl {
 
 pub(crate) fn init() {
     let intc = get_gicd();
+    debug!("Initializing GICD...");
     intc.lock().unwrap().open().unwrap();
     debug!("GICD initialized");
 }
 
 pub(crate) fn init_current_cpu() {
     let intc = rdrive::get_one::<Intc>().expect("no interrupt controller found");
-    let cpu_if = intc.lock().unwrap().cpu_local().unwrap();
+    let mut cpu_if = intc.lock().unwrap().cpu_local().unwrap();
+    cpu_if.open().unwrap();
     cpu_if.set_eoi_mode(true);
     CPU_IF.init_once(cpu_if);
     debug!("GIC initialized for current CPU");
@@ -115,3 +96,51 @@ fn get_gicd() -> Device<Intc> {
 fn current_cpu() -> usize {
     MPIDR_EL1.get() as usize & 0xffffff
 }
+
+pub(crate) fn set_enable(
+    irq_raw: usize,
+    is_private: bool,
+    trigger: Option<Trigger>,
+    enabled: bool,
+) {
+    debug!(
+        "IRQ({:#x}) set enable: {}, {}",
+        irq_raw,
+        enabled,
+        match trigger {
+            Some(t) => format!("trigger: {:?}", t),
+            None => String::new(),
+        }
+    );
+    let irq: IrqId = irq_raw.into();
+    if is_irq_private(irq_raw)
+        && let local::Capability::ConfigLocalIrq(c) = CPU_IF.capability()
+    {
+        if enabled {
+            c.irq_enable(irq).expect("failed to enable local IRQ");
+        } else {
+            c.irq_disable(irq).expect("failed to disable local IRQ");
+        }
+        if let Some(t) = trigger {
+            c.set_trigger(irq, t)
+                .expect("failed to set local IRQ trigger");
+        }
+    } else {
+        let mut intc = get_gicd().lock().unwrap();
+        if enabled {
+            intc.irq_enable(irq).expect("failed to enable IRQ");
+            if !is_irq_private(irq_raw) {
+                // For private IRQs, we need to acknowledge the interrupt
+                // controller.
+                intc.set_target_cpu(irq, current_cpu().into());
+            }
+
+            if let Some(t) = trigger {
+                intc.set_trigger(irq, t).expect("failed to set IRQ trigger");
+            }
+        } else {
+            intc.irq_disable(irq).expect("failed to disable IRQ");
+        }
+    }
+    debug!("IRQ({:#x}) set enable done", irq_raw);
+}

platforms/axplat-aarch64-dyn/src/lib.rs

@@ -10,6 +10,7 @@ use pie_boot::BootInfo;
 mod console;
 mod driver;
 mod init;
+#[cfg(feature = "irq")]
 mod irq;
 mod mem;
 mod power;

platforms/axplat-aarch64-dyn/src/power.rs

@@ -4,10 +4,7 @@ use aarch64_cpu::asm::wfi;
 use alloc::{boxed::Box, format};
 use axplat::power::PowerIf;
 use log::{debug, error};
-use rdrive::{
-    DriverGeneric, KError, PlatformDevice, driver::power::Interface, module_driver,
-    probe::OnProbeError, register::FdtInfo,
-};
+use rdrive::{PlatformDevice, module_driver, probe::OnProbeError, register::FdtInfo};
 use smccc::{Hvc, Smc, psci};
 use spin::Once;
 
@@ -71,31 +68,6 @@ impl TryFrom<&str> for Method {
     }
 }
 
-struct Psci {
-    method: Method,
-}
-
-impl DriverGeneric for Psci {
-    fn open(&mut self) -> Result<(), KError> {
-        Ok(())
-    }
-
-    fn close(&mut self) -> Result<(), KError> {
-        Ok(())
-    }
-}
-
-impl Interface for Psci {
-    fn shutdown(&mut self) {
-        if let Err(e) = match self.method {
-            Method::Smc => psci::system_off::<Smc>(),
-            Method::Hvc => psci::system_off::<Hvc>(),
-        } {
-            error!("shutdown failed: {}", e);
-        }
-    }
-}
-
 fn probe(fdt: FdtInfo<'_>, _dev: PlatformDevice) -> Result<(), OnProbeError> {
     let method = fdt
         .node

platforms/axplat-aarch64-dyn/src/time.rs

@@ -1,5 +1,11 @@
 use aarch64_cpu::registers::*;
 use axplat::time::TimeIf;
+use lazyinit::LazyInit;
+#[cfg(not(feature = "irq"))]
+use rdrive::driver::intc::Trigger;
+use rdrive::{IrqConfig, PlatformDevice, module_driver, probe::OnProbeError, register::FdtInfo};
+
+static TIMER_IRQ_CONFIG: LazyInit<IrqConfig> = LazyInit::new();
 
 struct TimeIfImpl;
 
@@ -34,6 +40,7 @@ impl TimeIf for TimeIfImpl {
     ///
     /// A timer interrupt will be triggered at the specified monotonic time
     /// deadline (in nanoseconds).
+    #[cfg(feature = "irq")]
     fn set_oneshot_timer(deadline_ns: u64) {
         let cnptct = CNTPCT_EL0.get();
         let cnptct_deadline = Self::nanos_to_ticks(deadline_ns);
@@ -45,4 +52,56 @@ impl TimeIf for TimeIfImpl {
             CNTP_TVAL_EL0.set(0);
         }
     }
+
+    #[cfg(feature = "irq")]
+    fn irq_num() -> usize {
+        TIMER_IRQ_CONFIG.irq.into()
+    }
+}
+
+#[cfg(feature = "irq")]
+/// Enable timer interrupts.
+///
+/// It should be called on all CPUs, as the timer interrupt is a PPI (Private
+/// Peripheral Interrupt).
+pub fn enable_irqs() {
+    CNTP_CTL_EL0.write(CNTP_CTL_EL0::ENABLE::SET);
+    CNTP_TVAL_EL0.set(0);
+    crate::irq::set_enable(
+        TIMER_IRQ_CONFIG.irq.into(),
+        true,
+        Some(TIMER_IRQ_CONFIG.trigger),
+        false,
+    );
+}
+
+module_driver!(
+    name: "ARMv8 Timer",
+    level: ProbeLevel::PreKernel,
+    priority: ProbePriority::DEFAULT,
+    probe_kinds: &[
+        ProbeKind::Fdt {
+            compatibles: &["arm,armv8-timer"],
+            on_probe: probe
+        }
+    ],
+);
+
+fn probe(_fdt: FdtInfo<'_>, _dev: PlatformDevice) -> Result<(), OnProbeError> {
+    #[cfg(not(feature = "irq"))]
+    let irq = IrqConfig {
+        irq: 0.into(),
+        trigger: Trigger::EdgeBoth,
+        is_private: true,
+    };
+    #[cfg(feature = "irq")]
+    let irq = {
+        #[cfg(not(feature = "hv"))]
+        let irq_idx = 1;
+        #[cfg(feature = "hv")]
+        let irq_idx = 3;
+        _dev.descriptor.irqs[irq_idx].clone()
+    };
+    TIMER_IRQ_CONFIG.call_once(|| irq);
+    Ok(())
 }