Initial RISC-V implementation

Has no IRQ handling yet

Author: tea

.gitmodules

@@ -1,7 +1,3 @@
-[submodule "syscall"]
-	path = syscall
-	url = https://gitlab.redox-os.org/redox-os/syscall.git
-	branch = master
 [submodule "slab_allocator"]
 	path = slab_allocator
 	url = https://gitlab.redox-os.org/redox-os/slab_allocator

Cargo.lock

@@ -16,7 +16,7 @@ hashbrown = { version = "0.14.3", default-features = false, features = ["ahash",
 linked_list_allocator = "0.9.0"
 log = "0.4"
 redox-path = "0.2.0"
-redox_syscall = { path = "syscall", default-features = false }
+redox_syscall = { git = "https://gitlab.redox-os.org/redox-os/syscall.git", branch = "master", default-features = false }
 slab_allocator = { path = "slab_allocator", optional = true }
 spin = "0.9.8"
 spinning_top = { version = "0.3", features = ["arc_lock"] }
@@ -35,7 +35,7 @@ features = ["elf32", "elf64"]
 version = "0.1.16"
 default-features = false
 
-[target.'cfg(target_arch = "aarch64")'.dependencies]
+[target.'cfg(any(target_arch = "aarch64", target_arch = "riscv64"))'.dependencies]
 byteorder = { version = "1", default-features = false }
 fdt = { git = "https://github.com/repnop/fdt.git", rev = "2fb1409edd1877c714a0aa36b6a7c5351004be54" }
 

Cargo.toml

@@ -88,6 +88,9 @@ fn main() {
                 panic!("nasm failed with exit status {}", status);
             }
         }
+        "riscv64" => {
+            println!("cargo:rustc-cfg=dtb");
+        }
         _ => (),
     }
 

build.rs

@@ -0,0 +1,68 @@
+ENTRY(kstart)
+OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv" )
+
+KERNEL_OFFSET = 0xFFFFFF0000000000;
+
+SECTIONS {
+    . = KERNEL_OFFSET;
+
+    . += SIZEOF_HEADERS;
+
+    /* Force the zero page to be part of a segment by creating a
+     * dummy section in the zero page.
+     * Linker will map the segment with the lowest vaddr value at
+     * 0xFFFFFF0000000000 even if the segment has a higher vaddr.
+     * As such without the zero page being part of a segment, the
+     * kernel would be loaded at an offset from the expected
+     * location. As the redox kernel is not currently relocatable,
+     * this would result in a crash. A similar issue likely exists
+     * with multiboot/multiboot2 and the paddr of the segment.
+     */
+    .dummy ALIGN(8) : AT(ADDR(.dummy) - KERNEL_OFFSET) {}
+
+    . = ALIGN(4096);
+
+    .text : AT(ADDR(.text) - KERNEL_OFFSET) {
+        __text_start = .;
+	*(.early_init.text*)
+	. = ALIGN(4096);
+        *(.text*)
+        __usercopy_start = .;
+        *(.usercopy-fns)
+        __usercopy_end = .;
+	. = ALIGN(4096);
+        __text_end = .;
+    }
+
+    .rodata : AT(ADDR(.rodata) - KERNEL_OFFSET) {
+        __rodata_start = .;
+        *(.rodata*)
+	. = ALIGN(4096);
+        __rodata_end = .;
+    }
+
+    .data : AT(ADDR(.data) - KERNEL_OFFSET) {
+        __data_start = .;
+        *(.data*)
+        *(.sdata*)
+	. = ALIGN(4096);
+        __data_end = .;
+        *(.got*)
+	. = ALIGN(4096);
+        __bss_start = .;
+        *(.bss*)
+        *(.sbss*)
+	. = ALIGN(4096);
+        __bss_end = .;
+    }
+
+    __end = .;
+
+    /DISCARD/ : {
+        *(.comment*)
+        *(.eh_frame*)
+        *(.gcc_except_table*)
+        *(.note*)
+        *(.rel.eh_frame*)
+    }
+}

linkers/riscv64.ld

@@ -31,7 +31,7 @@ pub unsafe fn init_early(dtb: &Fdt) {
         return;
     }
 
-    if let Some((phys, _size, skip_init, cts)) = diag_uart_range(dtb) {
+    if let Some((phys, _size, skip_init, cts, _)) = diag_uart_range(dtb) {
         let virt = crate::PHYS_OFFSET + phys;
         {
             let mut serial_port = SerialPort::new(virt, skip_init, cts);

src/arch/aarch64/device/serial.rs

@@ -19,3 +19,9 @@ pub use self::x86_64::*;
 #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
 #[macro_use]
 mod x86_shared;
+
+#[cfg(target_arch = "riscv64")]
+#[macro_use]
+pub mod riscv64;
+#[cfg(target_arch = "riscv64")]
+pub use self::riscv64::*;