IIUC, ARMv8-A LSE2 (Large System Extension 2) enables atomic misaligned reads that "fit in cachelines", and that seems to affect the model in minor ways — it seems the "storage" model reflects properties of caches and not just RAM.
For instance, a LDP instruction can read the the 64-bit value at address range [0x4, 0x12[ atomically — but only if the memory has inner & outer writeback cacheability.
- If your RAM model forbids such a misaligned access, LSE2 requires allowing that, at least sometimes.
- If your RAM model always allows such a misaligned access, no change is needed for LSE2 — that just seems a bit odd, and it means storage behavior accounts for some effects of caches as well.
References.
This is documented in prose in DDI0487 I.a, Sec. B2.5.2 Alignment of data accesses.
This is also documented in the DDI0487 I.a pseudocode (but not in DDI0487 G.a): function aarch64/functions/memory/AArch64.MemSingle (in Appendix J-1) will let CheckSingleAccessAttributes decide to split the access.
IIUC, ARMv8-A LSE2 (Large System Extension 2) enables atomic misaligned reads that "fit in cachelines", and that seems to affect the model in minor ways — it seems the "storage" model reflects properties of caches and not just RAM.
For instance, a LDP instruction can read the the 64-bit value at address range
[0x4, 0x12[atomically — but only if the memory has inner & outer writeback cacheability.References.
This is documented in prose in DDI0487 I.a, Sec. B2.5.2 Alignment of data accesses.
This is also documented in the DDI0487 I.a pseudocode (but not in DDI0487 G.a): function
aarch64/functions/memory/AArch64.MemSingle(in Appendix J-1) will letCheckSingleAccessAttributesdecide to split the access.