I have been working on setting up the NVMe CSD firmware on the CM3588 + NAS Kit and wanted to reach out for some help.
Hardware Setup:
- CSD: FriendlyElec CM3588 + NAS Kit
- Host PC: Dell OptiPlex 7050 (Intel Core i7, Intel Q270 chipset)
- Host OS: Ubuntu 25.10
-PCIe connection:
- M.2 to USB3 PCIe riser on the CM3588 side
- M.2 1-to-4 PCIe switch (ASMedia ASM1184e) on the host PC side
- connected via 45cm USB3 cable
Build:
The only change I made from the original build instructions was downgrading GCC to version 12 on Ubuntu 25.10, as GCC 15 caused host tool compilation errors. This was the error I got after running the build commands for the CM3588 board.
The build completed successfully afterwards. I just downloaded GCC 12 and changed the /usr/bin/gcc system pointer to it.
Issue:
The PCIe endpoint link never establishes between the CM3588 and the host PC. I connected through Uart and the boot log consistently shows:
rockchip-dw-pcie a40400000.pcie: Phy link never came up
I noticed in issue #6 you mentioned having issues with Intel Q270 chipsets and that it is "impossible to get the link stable". I am planning on using a newer generation Intel chip or an ARM chip, but I wanted to confirm that it my hardware connectivity is not the problem, but the Q270 chip set was.
Thank you for your work on this project and any help you can provide.
I have been working on setting up the NVMe CSD firmware on the CM3588 + NAS Kit and wanted to reach out for some help.
Hardware Setup:
-PCIe connection:
Build:
The only change I made from the original build instructions was downgrading GCC to version 12 on Ubuntu 25.10, as GCC 15 caused host tool compilation errors. This was the error I got after running the build commands for the CM3588 board.
The build completed successfully afterwards. I just downloaded GCC 12 and changed the /usr/bin/gcc system pointer to it.
Issue:
The PCIe endpoint link never establishes between the CM3588 and the host PC. I connected through Uart and the boot log consistently shows:
rockchip-dw-pcie a40400000.pcie: Phy link never came upI noticed in issue #6 you mentioned having issues with Intel Q270 chipsets and that it is "impossible to get the link stable". I am planning on using a newer generation Intel chip or an ARM chip, but I wanted to confirm that it my hardware connectivity is not the problem, but the Q270 chip set was.
Thank you for your work on this project and any help you can provide.