Hi all,
According to the Zvfbfa specification:
When altfmt=1 and SEW=8, all vector floating-point instructions are reserved except the instructions listed below, which are redefined to use the BF16 format for operands that would otherwise use FP16:
vfwcvt.f.x[u].v
vfncvt.x[u].f.w
vfncvt.rtz.x[u].f.w
When altfmt=1 and SEW=16, all vector floating-point instructions are reserved except the same set of instructions, which are also redefined to use the BF16 format for operands that would otherwise use FP16.
Based on my understanding, these instructions must validate the legal altfmt/SEW configurations as defined in the spec. However, I haven’t found any corresponding validation checks in the implementation.
For example, in vfncvt_x_f_w.h:
VI_VFP_NCVT_FP_TO_INT(
{ vd = P.VU.altfmt ? bf16_to_i8(vs2, softfloat_roundingMode, true)
: f16_to_i8(vs2, softfloat_roundingMode, true); }, // BODY16
{ vd = f32_to_i16(vs2, softfloat_roundingMode, true); }, // BODY32
{ vd = f64_to_i32(vs2, softfloat_roundingMode, true); }, // BODY64
{ require_zvfbfa_or_zvfh; }, // CHECK16
{ require(p->get_isa().get_zvf()); }, // CHECK32
{ require(p->get_isa().get_zvd()); }, // CHECK64
int // sign
)
Could someone please double-check this for me? Thanks!
Hi all,
According to the Zvfbfa specification:
Based on my understanding, these instructions must validate the legal altfmt/SEW configurations as defined in the spec. However, I haven’t found any corresponding validation checks in the implementation.
For example, in
vfncvt_x_f_w.h:Could someone please double-check this for me? Thanks!