diff --git a/coverage/dataset.cgf b/coverage/dataset.cgf index b84b69dd89..31bfc53788 100644 --- a/coverage/dataset.cgf +++ b/coverage/dataset.cgf @@ -171,6 +171,24 @@ datasets: x28: 0 x30: 0 + pair_regs_zilsd: &pair_regs_zilsd + x0: 0 + x2: 0 + x4: 0 + x6: 0 + x8: 0 + x10: 0 + x12: 0 + x14: 0 + x16: 0 + x18: 0 + x20: 0 + x22: 0 + x24: 0 + x26: 0 + x28: 0 + x30: 0 + c_regs: &c_regs x8: 0 x9: 0 @@ -256,6 +274,28 @@ datasets: x30: 0 x31: 0 + c_pair_regs: &c_pair_regs + x8: 0 + x10: 0 + x12: 0 + x14: 0 + + c_pair_regs_mx2: &c_pair_regs_mx2 + x4: 0 + x6: 0 + x8: 0 + x10: 0 + x12: 0 + x14: 0 + x16: 0 + x18: 0 + x20: 0 + x22: 0 + x24: 0 + x26: 0 + x28: 0 + x30: 0 + cbfmt_immval_sgn: &cbfmt_immval_sgn 'imm_val == (-2**(6-1))': 0 'imm_val == 0': 0 diff --git a/coverage/zilsd/rv32zilsd.cgf b/coverage/zilsd/rv32zilsd.cgf new file mode 100644 index 0000000000..d92a0a5944 --- /dev/null +++ b/coverage/zilsd/rv32zilsd.cgf @@ -0,0 +1,128 @@ +# See License https://gitlab.com/vyoma_systems/common/-/blob/main/LICENSE.BSD3.vyoma for more details + +ld: + config: + - check ISA:=regex(.*I.*Zilsd.*) + opcode: + ldz: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *pair_regs_zilsd + op_comb: + <<: *ifmt_op_comb + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1': 0 + 'ea_align == 0 and (imm_val % 8) == 2': 0 + 'ea_align == 0 and (imm_val % 8) == 3': 0 + 'ea_align == 0 and (imm_val % 8) == 4': 0 + 'ea_align == 0 and (imm_val % 8) == 5': 0 + 'ea_align == 0 and (imm_val % 8) == 6': 0 + 'ea_align == 0 and (imm_val % 8) == 7': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + + +sd: + config: + - check ISA:=regex(.*I.*Zilsd.*) + opcode: + sdz: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs_zilsd + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'ea_align == 0 and (imm_val % 8) == 0': 0 + 'ea_align == 0 and (imm_val % 8) == 1': 0 + 'ea_align == 0 and (imm_val % 8) == 2': 0 + 'ea_align == 0 and (imm_val % 8) == 3': 0 + 'ea_align == 0 and (imm_val % 8) == 4': 0 + 'ea_align == 0 and (imm_val % 8) == 5': 0 + 'ea_align == 0 and (imm_val % 8) == 6': 0 + 'ea_align == 0 and (imm_val % 8) == 7': 0 + 'imm_val > 0': 0 + 'imm_val < 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + + + +cldsp: + config: + - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*) + opcode: + c.ldspz: 0 + rd: + <<: *pair_regs + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +csdsp: + config: + - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*) + opcode: + c.sdspz: 0 + rs2: + <<: *pair_regs_zilsd + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0 + +cld: + config: + - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*) + opcode: + c.ldz: 0 + rs1: + <<: *c_regs + rd: + <<: *c_pair_regs + op_comb: + 'rs1 == rd': 0 + 'rs1 != rd': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + abstract_comb: + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 + +csd: + config: + - check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*) + opcode: + c.sdz: 0 + rs1: + <<: *c_regs + rs2: + <<: *c_pair_regs + op_comb: + 'rs1 != rs2': 0 + val_comb: + 'imm_val > 0': 0 + 'imm_val == 0': 0 + <<: [ *base_rs2val_sgn] + abstract_comb: + <<: [*rs2val_walking] + 'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0 + 'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0 diff --git a/coverage/zilsd/rv32zilsd_priv.cgf b/coverage/zilsd/rv32zilsd_priv.cgf new file mode 100644 index 0000000000..77be215b9c --- /dev/null +++ b/coverage/zilsd/rv32zilsd_priv.cgf @@ -0,0 +1,39 @@ +misalign-sd: + config: + - check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*32.*I.*Zicsr.*) + mnemonics: + sdz: 0 + rs1: + <<: *all_regs_mx0 + rs2: + <<: *pair_regs_zilsd + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + 'ea_align == 4': 0 + 'ea_align == 5': 0 + 'ea_align == 6': 0 + 'ea_align == 7': 0 + +misalign-ld: + config: + - check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True + - check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True + cond: check ISA:=regex(.*32.*I.*Zicsr.*) + mnemonics: + ldz: 0 + rs1: + <<: *all_regs_mx0 + rd: + <<: *pair_regs_zilsd + val_comb: + 'ea_align == 1': 0 + 'ea_align == 2': 0 + 'ea_align == 3': 0 + 'ea_align == 4': 0 + 'ea_align == 5': 0 + 'ea_align == 6': 0 + 'ea_align == 7': 0 diff --git a/riscv-ctg/riscv_ctg/constants.py b/riscv-ctg/riscv_ctg/constants.py index 5cff5e5427..fb3f957504 100644 --- a/riscv-ctg/riscv_ctg/constants.py +++ b/riscv-ctg/riscv_ctg/constants.py @@ -193,7 +193,7 @@ def gen_bitmanip_dataset(bit_width,sign=True): # increment each value in dataset, increment each value in dataset, add them to the dataset return dataset + [x - 1 for x in dataset] + [x+1 for x in dataset] + dataset0 -template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml"] +template_fnames = ["template.yaml","imc.yaml","fd.yaml","inx.yaml","zilsd.yaml"] template_files = [os.path.join(root,"data/"+f) for f in template_fnames] diff --git a/riscv-ctg/riscv_ctg/data/template.yaml b/riscv-ctg/riscv_ctg/data/template.yaml index 40d23c717b..668c883ab2 100644 --- a/riscv-ctg/riscv_ctg/data/template.yaml +++ b/riscv-ctg/riscv_ctg/data/template.yaml @@ -7,6 +7,9 @@ metadata: c_fregs: &c_fregs "['x'+str(x) for x in range(8,16)]" pair_regs: &pair_regs "['x'+str(x) for x in range(2,32 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" rv32rv64pair_regs: &rv32rv64pair_regs "['x'+str(x) for x in range(2,30 if 'e' not in base_isa else 16, 2)]" + pair_regs_zclsd: &pair_regs_zclsd "['x'+str(x) for x in range(2,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" + pair_regs_zilsd: &pair_regs_zilsd "['x'+str(x) for x in range(0,31 if 'e' not in base_isa else 16, 2 if xlen == 32 else 1)]" + c_pair_regs: &c_pair_regs "['x'+str(x) for x in range(8,16,2)]" aes32dsi: sig: diff --git a/riscv-ctg/riscv_ctg/data/zilsd.yaml b/riscv-ctg/riscv_ctg/data/zilsd.yaml new file mode 100644 index 0000000000..2877ed9aa7 --- /dev/null +++ b/riscv-ctg/riscv_ctg/data/zilsd.yaml @@ -0,0 +1,128 @@ +# See https://gitlab.com/vyoma_systems/common/-/blob/main/LICENSE.BSD3.vyoma for more details +ldz: + sig: + stride: 2 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rd_op_data: *pair_regs_zilsd + rd_hi: 0 + isa: + - IZilsd + xlen: [32] + opcode: ld + std_op: + formattype: 'iformat' + ea_align_data: '[0,1,2,3,4,5,6,7]' + imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + template: |- + + // $comment + // opcode:$opcode op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align;rd_hi:$rd_hi + TEST_LOAD_ZILSD($swreg,$testreg,$index,$rs1,$rd,$rd_hi,$imm_val,$offset,ld,$ea_align) + +sdz: + sig: + stride: 2 + sz: 'XLEN/8' + rs1_op_data: *all_regs_mx0 + rs2_op_data: *pair_regs_zilsd + rd_op_data: *all_regs + rs2_hi: 0 + xlen: [32] + opcode: sd + std_op: + isa: + - IZilsd + formattype: 'szformat' + ea_align_data: '[0,1,2,3,4,5,6,7]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: 'gen_sign_dataset(12)' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen,True)' + rs2_hi_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode:$opcode; op1:$rs1; op2:$rs2; op2val:$rs2_val;op3val:$rs2_hi_val; immval:$imm_val; align:$ea_align; rs2_hi:$rs2_hi + TEST_STORE_ZILSD($swreg,$testreg,$index,$rs1,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,sd,$ea_align) + +c.ldz: + sig: + stride: 2 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rd_op_data: *c_pair_regs + rd_hi: 0 + xlen: [32] + std_op: + isa: + - ICZilsd_Zclsd + formattype: 'clformat' + rs1_val_data: '[0]' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + template: |- + + // $comment + // opcode: $inst; op1:$rs1; dest:$rd; op1val:$rs1_val; immval:$imm_val; rd_hi:$rd_hi + TEST_LOAD_ZILSD($swreg,$testreg,$index,$rs1,$rd,$rd_hi,$imm_val,$offset,c.ld,$rs1_val) + +c.ldspz: + sig: + stride: 2 + sz: 'XLEN/8' + rd_op_data: *pair_regs_zclsd + rd_hi: 0 + xlen: [32] + std_op: + isa: + - ICZilsd_Zclsd + formattype: 'ciformat' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + rs1_val_data: 'gen_sign_dataset(xlen)+ gen_sp_dataset(xlen)' + template: |- + + // $comment + // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; rd_hi:$rd_hi + TEST_LOAD_ZILSD($swreg,$testreg,$index,x2,$rd,$rd_hi,$imm_val,$offset,c.ldsp,0) + +c.sdz: + sig: + stride: 2 + sz: 'XLEN/8' + rs1_op_data: *c_regs + rs2_op_data: *c_pair_regs + rs2_hi: 0 + xlen: [32] + std_op: + isa: + - ICZilsd_Zclsd + formattype: 'cszformat' + rs1_val_data: '[0]' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(5)]' + rs2_hi_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode:$inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; op3val:$rs2_hi_val; $immval:$imm_val; rs2_hi:$rs2_hi + TEST_STORE_ZILSD($swreg,$testreg,$index,$rs1,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,c.sd,0) + +c.sdspz: + sig: + stride: 2 + sz: 'XLEN/8' + rs2_op_data: *pair_regs_zilsd + rs2_hi: 0 + xlen: [32] + std_op: + isa: + - ICZilsd_Zclsd + formattype: 'csszformat' + rs2_val_data: 'gen_sign_dataset(xlen)' + imm_val_data: '[x*8 for x in gen_usign_dataset(6)]' + rs2_hi_val_data: 'gen_sign_dataset(xlen)' + template: |- + + // $comment + // opcode:$inst; op1:x2; op2:$rs2; op2val:$rs2_val; op3val:$rs2_hi_val; immval:$imm_val; rs2_hi:$rs2_hi + TEST_STORE_ZILSD($swreg,$testreg,$index,x2,$rs2,$rs2_hi,$rs2_val,$rs2_hi_val,$imm_val,$offset,c.sdsp,0) diff --git a/riscv-ctg/riscv_ctg/dsp_function.py b/riscv-ctg/riscv_ctg/dsp_function.py index 4b0f12bd01..46cdd3b3a3 100644 --- a/riscv-ctg/riscv_ctg/dsp_function.py +++ b/riscv-ctg/riscv_ctg/dsp_function.py @@ -151,6 +151,12 @@ def incr_reg_num(reg): num = num + 1 return name + str(num) +def dec_reg_num(reg): + name = reg[0] + num = int(reg[1:]) + num = num - 2 + return name + str(num) + def gen_pair_reg_data(instr_dict, xlen, _bit_width, p64_profile): ''' This function generate high registers for paired register operands, rs1_hi, rs2_hi and rd_hi depending on the specification of the p64_profile string. diff --git a/riscv-ctg/riscv_ctg/generator.py b/riscv-ctg/riscv_ctg/generator.py index 1253cfb5da..98b4ecadf9 100644 --- a/riscv-ctg/riscv_ctg/generator.py +++ b/riscv-ctg/riscv_ctg/generator.py @@ -36,6 +36,8 @@ one_operand_dinstructions += ["fround.d", "froundnx.d"] two_operand_dinstructions += ["fmaxm.d", "fminm.d", "fleq.d", "fltq.d"] +#Zilsd +zilsd_instructions = ["ldz","sdz","c.ldz","c.sdz","c.ldspz","c.sdspz"] def is_fp_instruction(insn): ''' @@ -71,6 +73,7 @@ def get_rm(opcode): 'r4format': ['rs1', 'rs2', 'rs3', 'rd'], 'iformat': ['rs1', 'rd'], 'sformat': ['rs1', 'rs2'], + 'szformat': ['rs1', 'rs2'], 'bsformat': ['rs1', 'rs2', 'rd'], 'bformat': ['rs1', 'rs2'], 'uformat': ['rd'], @@ -79,9 +82,11 @@ def get_rm(opcode): 'cmvformat': ['rd', 'rs2'], 'ciformat': ['rd'], 'cssformat': ['rs2'], + 'csszformat': ['rs2'], 'ciwformat': ['rd'], 'clformat': ['rs1', 'rd'], 'csformat': ['rs1', 'rs2'], + 'cszformat': ['rs1', 'rs2'], 'caformat': ['rs1', 'rs2'], 'cuformat': ['rs1'], 'cbformat': ['rs1'], @@ -126,6 +131,7 @@ def get_rm(opcode): (['rs{0}_sgn_prefix'.format(x) for x in range(1,4)] if is_sgn_extd else [])", 'iformat': "['rs1_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])", 'sformat': "['rs1_val', 'rs2_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])", + 'szformat': "['rs1_val', 'rs2_val', 'rs2_hi_val', 'imm_val'] + ([] if not is_fext else ['fcsr'])", 'bsformat': "['rs1_val', 'rs2_val', 'imm_val']", 'bformat': "['rs1_val', 'rs2_val', 'imm_val']", 'uformat': "['imm_val']", @@ -134,6 +140,7 @@ def get_rm(opcode): 'cmvformat': "['rs2_val']", 'ciformat': "['rs1_val', 'imm_val']", 'cssformat': "['rs2_val', 'imm_val']", + 'csszformat': "['rs2_val', 'rs2_hi_val', 'imm_val']", 'ciwformat': "['imm_val']", 'clformat': "['rs1_val', 'imm_val', 'fcsr']", 'cuformat': "['rs1_val']", @@ -142,6 +149,7 @@ def get_rm(opcode): 'csbformat': "['rs1_val','rs2_val','imm_val']", 'cshformat': "['rs1_val','rs2_val','imm_val']", 'csformat': "['rs1_val', 'rs2_val', 'imm_val']", + 'cszformat': "['rs1_val', 'rs2_val', 'rs2_hi_val', 'imm_val']", 'caformat': "['rs1_val', 'rs2_val']", 'cbformat': "['rs1_val', 'imm_val']", 'cjformat': "['imm_val']", @@ -281,7 +289,7 @@ def __init__(self,fmt,opnode,opcode,randomization, xl, fl, ifl ,base_isa_str,inx self.inxFlag = inxFlag self.is_sgn_extd = is_sgn_extd - if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw","c.fld","c.flwsp","c.fswsp","c.fldsp","c.fsdsp"]: + if opcode in ['sw', 'sh', 'sb', 'lw', 'lhu', 'lh', 'lb', 'lbu', 'ld', 'lwu', 'sd',"jal","beq","bge","bgeu","blt","bltu","bne","jalr","c.jalr","c.jr","flw","fsw","fld","fsd","flh","fsh","c.lbu","c.lhu","c.lh","c.sb","c.sh","c.flw","c.fld","c.flwsp","c.fswsp","c.fldsp","c.fsdsp","ldz","sdz"]: self.val_vars = self.val_vars + ['ea_align'] self.template = opnode['template'] self.opnode = opnode @@ -814,7 +822,7 @@ def gen_inst(self,op_comb, val_comb, cgf): instr_dict.append(self.__clui_instr__(op,val)) elif self.opcode in ['c.beqz', 'c.bnez']: instr_dict.append(self.__cb_instr__(op,val)) - elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp','c.flwsp','c.fswsp','c.fldsp','c.fsdsp']: + elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp','c.ldspz','c.sdspz', 'c.flwsp','c.fswsp','c.fldsp','c.fsdsp']: if any([x == 'x2' for x in op]): cont.append(val) instr_dict.append(self.__cmemsp_instr__(op,val)) @@ -834,7 +842,7 @@ def gen_inst(self,op_comb, val_comb, cgf): instr_dict.append(self.__clui_instr__(op,val)) elif self.opcode in ['c.beqz', 'c.bnez','c.lbu','c.lhu','c.lh','c.sb','c.sh']: instr_dict.append(self.__cb_instr__(op,val)) - elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp','c.fsdsp','c.fswsp']: + elif self.opcode in ['c.lwsp', 'c.swsp', 'c.ldsp', 'c.sdsp','c.ldspz','c.sdspz','c.fsdsp','c.fswsp']: instr_dict.append(self.__cmemsp_instr__(op,val)) elif self.fmt == 'bformat' or self.opcode in ['c.j']: instr_dict.append(self.__bfmt_instr__(op,val)) @@ -919,7 +927,7 @@ def eval_inst_coverage(coverpoints,instr): for instr in instr_dict: unique = False skip_val = False - if instr['inst'] in cgf['mnemonics']: + if instr['inst'] in cgf['mnemonics'] or instr['inst'] in zilsd_instructions: if 'rs1' in instr and 'rs2' in instr: if instr['rs1'] == instr['rs2']: skip_val = True @@ -944,6 +952,14 @@ def eval_inst_coverage(coverpoints,instr): final_instr.append(instr) else: i+=1 + if instr['inst'] in zilsd_instructions: + if 'rs2_hi' and 'rd' not in instr : + instr.update({'rs2_hi': incr_reg_num(instr['rs2'])}) + if instr['rs2_hi'] == instr['rs1'] and instr['rs1'] == 'x31': + instr.update({'rs1': dec_reg_num(instr['rs1'])}) + elif 'rd_hi' not in instr and 'rd' in instr: + instr.update({'rd_hi': incr_reg_num(instr['rd'])}) + if any('IP' in isa for isa in self.opnode['isa']): if 'p64_profile' in self.opnode: diff --git a/riscv-isac/riscv_isac/InstructionObject.py b/riscv-isac/riscv_isac/InstructionObject.py index 2516f97e17..71e94021ee 100644 --- a/riscv-isac/riscv_isac/InstructionObject.py +++ b/riscv-isac/riscv_isac/InstructionObject.py @@ -1,7 +1,7 @@ import struct instrs_sig_mutable = ['auipc','jal','jalr'] -instrs_sig_update = ['sh','sb','sw','sd','c.fsw','c.sw','c.sd','c.swsp','c.sdsp','fsw','fsd',\ +instrs_sig_update = ['sh','sb','sw','sd','sdz','c.fsw','c.sw','c.sd','c.sdz','c.swsp','c.sdsp','c.sdspz','fsw','fsd',\ 'c.fsw','c.fsd','c.fswsp','c.fsdsp'] instrs_no_reg_tracking = ['beq','bne','blt','bge','bltu','bgeu','fence','c.j','c.jal','c.jalr',\ 'c.jr','c.beqz','c.bnez', 'c.ebreak'] + instrs_sig_update @@ -12,7 +12,7 @@ 'fmul.d','fdiv.d','fsqrt.d','fmin.d','fmax.d','fcvt.s.d','fcvt.d.s',\ 'feq.d','flt.d','fle.d','fcvt.w.d','fcvt.wu.d','fcvt.l.d','fcvt.lu.d',\ 'fcvt.d.l','fcvt.d.lu'] -unsgn_rs1 = ['sw','sd','sh','sb','ld','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd','flh','fsh',\ +unsgn_rs1 = ['sw','sd','sh','sb','ld','ldz','sdz','c.ldz','c.ldspz','c.sdz','c.sdspz','lw','lwu','lh','lhu','lb', 'lbu','flw','fld','fsw','fsd','flh','fsh',\ 'bgeu', 'bltu', 'sltiu', 'sltu','c.lw','c.lhu','c.lh','c.ld','c.lwsp','c.ldsp',\ 'c.sw','c.sd','c.swsp','c.sdsp','c.fsw','mulhu','divu','remu','divuw',\ 'remuw','aes64ds','aes64dsm','aes64es','aes64esm','aes64ks2',\ @@ -219,7 +219,7 @@ def evaluate_instr_vars(self, xlen, flen, arch_state, csr_regfile, instr_vars): ea_align = (rs1_val + imm_val) % 2 if self.instr_name in ['sw','sh','sb','lw','lhu','lh','lb','lbu','lwu','flw','fsw']: ea_align = (rs1_val + imm_val) % 4 - if self.instr_name in ['ld','sd','fld','fsd']: + if self.instr_name in ['ldz','sdz','ld','sd','fld','fsd']: ea_align = (rs1_val + imm_val) % 8 instr_vars.update({ diff --git a/riscv-isac/riscv_isac/coverage.py b/riscv-isac/riscv_isac/coverage.py index 330ea2141d..856653b02d 100644 --- a/riscv-isac/riscv_isac/coverage.py +++ b/riscv-isac/riscv_isac/coverage.py @@ -1553,7 +1553,7 @@ def get_key_from_value(dictionary, target_value): stats_queue.close() def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xlen, flen, addr_pairs - , dump, cov_labels, sig_addrs, window_size, inxFlg, elf, no_count=False, procs=1): + , dump, cov_labels, sig_addrs, window_size, inxFlg, elf, zilsdFlg, no_count=False, procs=1): '''Compute the Coverage''' global arch_state @@ -1627,6 +1627,7 @@ def compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xle decoder_pm.register(decoderclass()) decoder = decoder_pm.hook decoder.setup(inxFlag=inxFlg, arch="rv"+str(xlen)) + decoder.setupz(zilsdFlg=zilsdFlg, arch="rv"+str(xlen)) iterator = iter(parser.__iter__()[0]) diff --git a/riscv-isac/riscv_isac/isac.py b/riscv-isac/riscv_isac/isac.py index 7c42e2786e..7103a9c9ef 100644 --- a/riscv-isac/riscv_isac/isac.py +++ b/riscv-isac/riscv_isac/isac.py @@ -58,7 +58,7 @@ def preprocessing(cgf, header_file, cgf_macros): return cgf def isac(output_file,elf ,trace_file, window_size, cgf, parser_name, decoder_name, parser_path, decoder_path, detailed, test_labels, - sig_labels, dump, cov_labels, xlen, flen, no_count, procs, *inxFlg, logging=False): + sig_labels, dump, cov_labels, xlen, flen, zilsdFlg, no_count, procs, *inxFlg, logging=False): test_addr = [] sig_addr = [] if parser_path: @@ -89,7 +89,7 @@ def isac(output_file,elf ,trace_file, window_size, cgf, parser_name, decoder_nam sig_addr.append((start_address,end_address)) else: test_name = trace_file.rsplit(',',1)[0] - rpt = cov.compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xlen, flen, test_addr, dump, cov_labels, sig_addr, window_size, inxFlg, elf, no_count, procs) + rpt = cov.compute(trace_file, test_name, cgf, parser_name, decoder_name, detailed, xlen, flen, test_addr, dump, cov_labels, sig_addr, window_size, inxFlg, elf, zilsdFlg, no_count, procs) if output_file is not None and logging: logger.info('Coverage Report:') #logger.info('\n\n' + rpt) diff --git a/riscv-isac/riscv_isac/main.py b/riscv-isac/riscv_isac/main.py index d34de349cb..45d44680c5 100644 --- a/riscv-isac/riscv_isac/main.py +++ b/riscv-isac/riscv_isac/main.py @@ -145,15 +145,20 @@ def cli(verbose): help = "Log redundant coverpoints during normalization" ) @click.option('--inxFlg', 'inxFlg', - type=bool, - default = False, + type=bool, + default = False, help="Enable inxFlg if the extension is Z*inx" ) +@click.option('--zilsdFlg', 'zilsdFlg', + type=bool, + default = False, + help="Enable zilsdFlg if the extension is Zilsd" +) def coverage(elf,trace_file, header_file, window_size, cgf_file, detailed,parser_name, decoder_name, parser_path, decoder_path,output_file, test_label, - sig_label, dump,cov_label, cgf_macro, xlen, flen, no_count, procs, log_redundant, inxFlg): + sig_label, dump,cov_label, cgf_macro, xlen, flen, no_count, procs, log_redundant, inxFlg, zilsdFlg): isac(output_file,elf,trace_file, window_size, preprocessing(Translate_cgf(expand_cgf(cgf_file,int(xlen),int(flen),log_redundant)), header_file, cgf_macro), parser_name, decoder_name, parser_path, decoder_path, detailed, test_label, - sig_label, dump, cov_label, int(xlen), int(flen), no_count, procs, inxFlg, logging=False) + sig_label, dump, cov_label, int(xlen), int(flen), zilsdFlg, no_count, procs, inxFlg, logging=False) @cli.command(help = "Merge given coverage files.") @click.argument( diff --git a/riscv-isac/riscv_isac/plugins/internaldecoder.py b/riscv-isac/riscv_isac/plugins/internaldecoder.py index 5940993867..180d0f607f 100644 --- a/riscv-isac/riscv_isac/plugins/internaldecoder.py +++ b/riscv-isac/riscv_isac/plugins/internaldecoder.py @@ -409,7 +409,11 @@ def init_rvp_dictionary(self): @plugins.decoderHookImpl def setup(self, arch): self.arch = arch - + @plugins.decoderHookImpl + def setupz(self, zilsdFlg,arch: str): + self.arch = arch + self.zilsdFlg = zilsdFlg + FIRST2_MASK = 0x00000003 OPCODE_MASK = 0x0000007f FUNCT3_MASK = 0x00007000 @@ -530,6 +534,8 @@ def load_ops(self, instrObj): instrObj.instr_name = 'lwu' if funct3 == 0b011: instrObj.instr_name = 'ld' + if funct3 == 0b011 and self.arch == 'rv32' and self.zilsdFlg is True : + instrObj.instr_name = 'ldz' return instrObj @@ -554,6 +560,8 @@ def store_ops(self, instrObj): instrObj.instr_name = 'sw' if funct3 == 0b011: instrObj.instr_name = 'sd' + if funct3 == 0b011 and self.arch == 'rv32' and self.zilsdFlg is True : + instrObj.instr_name = 'sdz' return instrObj @@ -2097,7 +2105,12 @@ def quad0(self, instrObj): instrObj.imm = uimm_6_5_3_2 elif funct3 == 0b011: - if self.arch == 'rv32': + if self.arch == 'rv32' and self.zilsdFlg is True : + instrObj.instr_name = 'c.ldz' + instrObj.rd = (8 + rdprime, 'x') + instrObj.rs1 = (8 + rs1prime, 'x') + instrObj.imm = uimm_7_6_5_3 + elif self.arch == 'rv32': instrObj.instr_name = 'c.flw' instrObj.rd = (8 + rdprime, 'f') instrObj.rs1 = (8 + rs1prime, 'x') @@ -2121,7 +2134,12 @@ def quad0(self, instrObj): instrObj.imm = uimm_6_5_3_2 elif funct3 == 0b111: - if self.arch == 'rv32': + if self.arch == 'rv32' and self.zilsdFlg is True : + instrObj.instr_name = 'c.sdz' + instrObj.rs1 = (8 + rs1prime, 'x') + instrObj.rs2 = (8 + rs2prime, 'x') + instrObj.imm = uimm_7_6_5_3 + elif self.arch == 'rv32': instrObj.instr_name = 'c.fsw' instrObj.rs1 = (8 + rs1prime, 'x') instrObj.rs2 = (8 + rs2prime, 'f') @@ -2323,6 +2341,11 @@ def quad2(self, instrObj): instrObj.rs1 = (2, 'x') instrObj.rd = (rd, 'x') instrObj.imm = imm_lwsp + elif funct3 == 3 and self.arch == 'rv32' and self.zilsdFlg is True: + instrObj.instr_name = 'c.ldspz' + instrObj.rd = (rd, 'x') + instrObj.rs1 = (2, 'x') + instrObj.imm = imm_ldsp elif funct3 == 3 and self.arch == 'rv32': instrObj.instr_name = 'c.flwsp' instrObj.rd = (rd, 'f') @@ -2330,7 +2353,7 @@ def quad2(self, instrObj): instrObj.imm = imm_lwsp elif funct3 == 3 and self.arch == 'rv64': instrObj.instr_name = 'c.ldsp' - instrObj.rd = (rd, 'f') + instrObj.rd = (rd, 'x') instrObj.rs1 = (2, 'x') instrObj.imm = imm_ldsp elif funct3 == 4 and rs1 != 0 and imm_5 == 0 and rs2 == 0: @@ -2362,6 +2385,11 @@ def quad2(self, instrObj): instrObj.rs2 = (rs2, 'x') instrObj.imm = imm_swsp instrObj.rs1 = (2 , 'x') + elif funct3 == 7 and self.arch == 'rv32' and self.zilsdFlg is True: + instrObj.instr_name = 'c.sdspz' + instrObj.rs2 = (rs2, 'x') + instrObj.rs1 = (2, 'x') + instrObj.imm = imm_fsdsp elif funct3 == 7 and self.arch == 'rv32': instrObj.instr_name = 'c.fswsp' instrObj.rs2 = (rs2, 'f') diff --git a/riscv-test-suite/rv32i_m/Zilsd/src/cld-01.S b/riscv-test-suite/rv32i_m/Zilsd/src/cld-01.S new file mode 100644 index 0000000000..221ba3f1f0 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zilsd/src/cld-01.S @@ -0,0 +1,126 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Mar 25 08:20:56 2025 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/zilsd/rv32zilsd.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.ldz instruction of the RISC-V RV32CZilsd_Zclsd extension for the cld covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZilsd_Zclsd") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*);def TEST_CASE_1=True;",cld) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==x14, rd==x14, imm_val > 0, +// opcode: c.ldz; op1:x14; dest:x14; op1val:0x0; immval:0xf8; rd_hi:x15 +TEST_LOAD_ZILSD(x1,x2,0,x14,x14,x15,0xf8,0*XLEN/8,c.ld,0x0) + +inst_1: +// rs1 != rd, rs1==x15, rd==x12, imm_val == 0, +// opcode: c.ldz; op1:x15; dest:x12; op1val:0x0; immval:0x0; rd_hi:x13 +TEST_LOAD_ZILSD(x1,x2,0,x15,x12,x13,0x0,2*XLEN/8,c.ld,0x0) + +inst_2: +// rs1==x13, rd==x10, +// opcode: c.ldz; op1:x13; dest:x10; op1val:0x0; immval:0x0; rd_hi:x11 +TEST_LOAD_ZILSD(x1,x2,0,x13,x10,x11,0x0,4*XLEN/8,c.ld,0x0) + +inst_3: +// rs1==x12, rd==x8, +// opcode: c.ldz; op1:x12; dest:x8; op1val:0x0; immval:0x0; rd_hi:x9 +TEST_LOAD_ZILSD(x1,x2,0,x12,x8,x9,0x0,6*XLEN/8,c.ld,0x0) + +inst_4: +// rs1==x11, +// opcode: c.ldz; op1:x11; dest:x14; op1val:0x0; immval:0x0; rd_hi:x15 +TEST_LOAD_ZILSD(x1,x2,0,x11,x14,x15,0x0,8*XLEN/8,c.ld,0x0) + +inst_5: +// rs1==x10, +// opcode: c.ldz; op1:x10; dest:x14; op1val:0x0; immval:0x0; rd_hi:x15 +TEST_LOAD_ZILSD(x1,x2,0,x10,x14,x15,0x0,10*XLEN/8,c.ld,0x0) + +inst_6: +// rs1==x9, +// opcode: c.ldz; op1:x9; dest:x14; op1val:0x0; immval:0x0; rd_hi:x15 +TEST_LOAD_ZILSD(x1,x2,0,x9,x14,x15,0x0,12*XLEN/8,c.ld,0x0) + +inst_7: +// rs1==x8, +// opcode: c.ldz; op1:x8; dest:x14; op1val:0x0; immval:0x0; rd_hi:x15 +TEST_LOAD_ZILSD(x1,x2,0,x8,x14,x15,0x0,14*XLEN/8,c.ld,0x0) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 16*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zilsd/src/cldsp-01.S b/riscv-test-suite/rv32i_m/Zilsd/src/cldsp-01.S new file mode 100644 index 0000000000..2b88a8f3cc --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zilsd/src/cldsp-01.S @@ -0,0 +1,166 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Mar 25 08:20:56 2025 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/zilsd/rv32zilsd.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.ldspz instruction of the RISC-V RV32CZilsd_Zclsd extension for the cldsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZilsd_Zclsd") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*);def TEST_CASE_1=True;",cldsp) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rd==x30, imm_val > 0, +// opcode: c.ldspz; op1:x2; dest:x30; immval:0x1f8; rd_hi:x31 +TEST_LOAD_ZILSD(x1,x3,0,x2,x30,x31,0x1f8,0*XLEN/8,c.ldsp,0) + +inst_1: +// rd==x28, imm_val == 0, +// opcode: c.ldspz; op1:x2; dest:x28; immval:0x0; rd_hi:x29 +TEST_LOAD_ZILSD(x1,x3,0,x2,x28,x29,0x0,2*XLEN/8,c.ldsp,0) + +inst_2: +// rd==x26, +// opcode: c.ldspz; op1:x2; dest:x26; immval:0x0; rd_hi:x27 +TEST_LOAD_ZILSD(x1,x3,0,x2,x26,x27,0x0,4*XLEN/8,c.ldsp,0) + +inst_3: +// rd==x24, +// opcode: c.ldspz; op1:x2; dest:x24; immval:0x0; rd_hi:x25 +TEST_LOAD_ZILSD(x1,x3,0,x2,x24,x25,0x0,6*XLEN/8,c.ldsp,0) + +inst_4: +// rd==x22, +// opcode: c.ldspz; op1:x2; dest:x22; immval:0x0; rd_hi:x23 +TEST_LOAD_ZILSD(x1,x3,0,x2,x22,x23,0x0,8*XLEN/8,c.ldsp,0) + +inst_5: +// rd==x20, +// opcode: c.ldspz; op1:x2; dest:x20; immval:0x0; rd_hi:x21 +TEST_LOAD_ZILSD(x1,x3,0,x2,x20,x21,0x0,10*XLEN/8,c.ldsp,0) + +inst_6: +// rd==x18, +// opcode: c.ldspz; op1:x2; dest:x18; immval:0x0; rd_hi:x19 +TEST_LOAD_ZILSD(x1,x3,0,x2,x18,x19,0x0,12*XLEN/8,c.ldsp,0) + +inst_7: +// rd==x16, +// opcode: c.ldspz; op1:x2; dest:x16; immval:0x0; rd_hi:x17 +TEST_LOAD_ZILSD(x1,x3,0,x2,x16,x17,0x0,14*XLEN/8,c.ldsp,0) + +inst_8: +// rd==x14, +// opcode: c.ldspz; op1:x2; dest:x14; immval:0x0; rd_hi:x15 +TEST_LOAD_ZILSD(x1,x3,0,x2,x14,x15,0x0,16*XLEN/8,c.ldsp,0) + +inst_9: +// rd==x12, +// opcode: c.ldspz; op1:x2; dest:x12; immval:0x0; rd_hi:x13 +TEST_LOAD_ZILSD(x1,x3,0,x2,x12,x13,0x0,18*XLEN/8,c.ldsp,0) + +inst_10: +// rd==x10, +// opcode: c.ldspz; op1:x2; dest:x10; immval:0x0; rd_hi:x11 +TEST_LOAD_ZILSD(x1,x3,0,x2,x10,x11,0x0,20*XLEN/8,c.ldsp,0) + +inst_11: +// rd==x8, +// opcode: c.ldspz; op1:x2; dest:x8; immval:0x0; rd_hi:x9 +TEST_LOAD_ZILSD(x1,x3,0,x2,x8,x9,0x0,22*XLEN/8,c.ldsp,0) + +inst_12: +// rd==x6, +// opcode: c.ldspz; op1:x2; dest:x6; immval:0x0; rd_hi:x7 +TEST_LOAD_ZILSD(x1,x3,0,x2,x6,x7,0x0,24*XLEN/8,c.ldsp,0) + +inst_13: +// rd==x4, +// opcode: c.ldspz; op1:x2; dest:x4; immval:0x0; rd_hi:x5 +TEST_LOAD_ZILSD(x1,x3,0,x2,x4,x5,0x0,26*XLEN/8,c.ldsp,0) +RVTEST_SIGBASE(x1,signature_x1_2) + +inst_14: +// rd==x2, +// opcode: c.ldspz; op1:x2; dest:x2; immval:0x0; rd_hi:x3 +TEST_LOAD_ZILSD(x1,x3,0,x2,x2,x3,0x0,0*XLEN/8,c.ldsp,0) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_2: + .fill 2*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zilsd/src/csd-01.S b/riscv-test-suite/rv32i_m/Zilsd/src/csd-01.S new file mode 100644 index 0000000000..75384d4dc8 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zilsd/src/csd-01.S @@ -0,0 +1,126 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Mar 25 08:20:56 2025 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/zilsd/rv32zilsd.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.sdz instruction of the RISC-V RV32CZilsd_Zclsd extension for the csd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZilsd_Zclsd") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*);def TEST_CASE_1=True;",csd) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rs2, rs1==x15, rs2==x14, rs2_val == 1, imm_val == 0 +// opcode:c.sdz; op1:x15; op2:x14; op2val:0x1; op3val:-0x80000000; $immval:0x0; rs2_hi:x15 +TEST_STORE_ZILSD(x1,x2,0,x15,x14,x15,0x1,-0x80000000,0x0,0*XLEN/8,c.sd,0) + +inst_1: +// rs1==x14, rs2==x12, rs2_val == 0, +// opcode:c.sdz; op1:x14; op2:x12; op2val:0x0; op3val:-0x80000000; $immval:0x0; rs2_hi:x13 +TEST_STORE_ZILSD(x1,x2,0,x14,x12,x13,0x0,-0x80000000,0x0,2*XLEN/8,c.sd,0) + +inst_2: +// rs1==x13, rs2==x10, rs2_val == (2**(xlen-1)-1), +// opcode:c.sdz; op1:x13; op2:x10; op2val:0x7fffffff; op3val:-0x80000000; $immval:0x0; rs2_hi:x11 +TEST_STORE_ZILSD(x1,x2,0,x13,x10,x11,0x7fffffff,-0x80000000,0x0,4*XLEN/8,c.sd,0) + +inst_3: +// rs1==x12, rs2==x8, rs2_val == (-2**(xlen-1)), +// opcode:c.sdz; op1:x12; op2:x8; op2val:-0x80000000; op3val:-0x80000000; $immval:0x0; rs2_hi:x9 +TEST_STORE_ZILSD(x1,x2,0,x12,x8,x9,-0x80000000,-0x80000000,0x0,6*XLEN/8,c.sd,0) + +inst_4: +// rs1==x11, imm_val > 0, +// opcode:c.sdz; op1:x11; op2:x14; op2val:-0x80000000; op3val:-0x80000000; $immval:0xf8; rs2_hi:x15 +TEST_STORE_ZILSD(x1,x2,0,x11,x14,x15,-0x80000000,-0x80000000,0xf8,8*XLEN/8,c.sd,0) + +inst_5: +// rs1==x10, +// opcode:c.sdz; op1:x10; op2:x14; op2val:-0x80000000; op3val:-0x80000000; $immval:0x0; rs2_hi:x15 +TEST_STORE_ZILSD(x1,x2,0,x10,x14,x15,-0x80000000,-0x80000000,0x0,10*XLEN/8,c.sd,0) + +inst_6: +// rs1==x9, +// opcode:c.sdz; op1:x9; op2:x14; op2val:-0x80000000; op3val:-0x80000000; $immval:0x0; rs2_hi:x15 +TEST_STORE_ZILSD(x1,x2,0,x9,x14,x15,-0x80000000,-0x80000000,0x0,12*XLEN/8,c.sd,0) + +inst_7: +// rs1==x8, +// opcode:c.sdz; op1:x8; op2:x14; op2val:-0x80000000; op3val:-0x80000000; $immval:0x0; rs2_hi:x15 +TEST_STORE_ZILSD(x1,x2,0,x8,x14,x15,-0x80000000,-0x80000000,0x0,14*XLEN/8,c.sd,0) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 16*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zilsd/src/csdsp-01.S b/riscv-test-suite/rv32i_m/Zilsd/src/csdsp-01.S new file mode 100644 index 0000000000..54b5f1eb58 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zilsd/src/csdsp-01.S @@ -0,0 +1,171 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Mar 25 08:20:56 2025 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/zilsd/rv32zilsd.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the c.sdspz instruction of the RISC-V RV32CZilsd_Zclsd extension for the csdsp covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32ICZilsd_Zclsd") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*C.*Zilsd.*Zclsd.*);def TEST_CASE_1=True;",csdsp) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs2==x30, rs2_val == 1, imm_val == 0 +// opcode:c.sdspz; op1:x2; op2:x30; op2val:0x1; op3val:-0x80000000; immval:0x0; rs2_hi:x31 +TEST_STORE_ZILSD(x1,x3,0,x2,x30,x31,0x1,-0x80000000,0x0,0*XLEN/8,c.sdsp,0) + +inst_1: +// rs2==x28, rs2_val == 0, +// opcode:c.sdspz; op1:x2; op2:x28; op2val:0x0; op3val:-0x80000000; immval:0x0; rs2_hi:x29 +TEST_STORE_ZILSD(x1,x3,0,x2,x28,x29,0x0,-0x80000000,0x0,2*XLEN/8,c.sdsp,0) + +inst_2: +// rs2==x26, rs2_val == (2**(xlen-1)-1), +// opcode:c.sdspz; op1:x2; op2:x26; op2val:0x7fffffff; op3val:-0x80000000; immval:0x0; rs2_hi:x27 +TEST_STORE_ZILSD(x1,x3,0,x2,x26,x27,0x7fffffff,-0x80000000,0x0,4*XLEN/8,c.sdsp,0) + +inst_3: +// rs2==x24, rs2_val == (-2**(xlen-1)), +// opcode:c.sdspz; op1:x2; op2:x24; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x25 +TEST_STORE_ZILSD(x1,x3,0,x2,x24,x25,-0x80000000,-0x80000000,0x0,6*XLEN/8,c.sdsp,0) + +inst_4: +// rs2==x22, imm_val > 0, +// opcode:c.sdspz; op1:x2; op2:x22; op2val:-0x80000000; op3val:-0x80000000; immval:0x1f8; rs2_hi:x23 +TEST_STORE_ZILSD(x1,x3,0,x2,x22,x23,-0x80000000,-0x80000000,0x1f8,8*XLEN/8,c.sdsp,0) + +inst_5: +// rs2==x20, +// opcode:c.sdspz; op1:x2; op2:x20; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x21 +TEST_STORE_ZILSD(x1,x3,0,x2,x20,x21,-0x80000000,-0x80000000,0x0,10*XLEN/8,c.sdsp,0) + +inst_6: +// rs2==x18, +// opcode:c.sdspz; op1:x2; op2:x18; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x19 +TEST_STORE_ZILSD(x1,x3,0,x2,x18,x19,-0x80000000,-0x80000000,0x0,12*XLEN/8,c.sdsp,0) + +inst_7: +// rs2==x16, +// opcode:c.sdspz; op1:x2; op2:x16; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x17 +TEST_STORE_ZILSD(x1,x3,0,x2,x16,x17,-0x80000000,-0x80000000,0x0,14*XLEN/8,c.sdsp,0) + +inst_8: +// rs2==x14, +// opcode:c.sdspz; op1:x2; op2:x14; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x15 +TEST_STORE_ZILSD(x1,x3,0,x2,x14,x15,-0x80000000,-0x80000000,0x0,16*XLEN/8,c.sdsp,0) + +inst_9: +// rs2==x12, +// opcode:c.sdspz; op1:x2; op2:x12; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x13 +TEST_STORE_ZILSD(x1,x3,0,x2,x12,x13,-0x80000000,-0x80000000,0x0,18*XLEN/8,c.sdsp,0) + +inst_10: +// rs2==x10, +// opcode:c.sdspz; op1:x2; op2:x10; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x11 +TEST_STORE_ZILSD(x1,x3,0,x2,x10,x11,-0x80000000,-0x80000000,0x0,20*XLEN/8,c.sdsp,0) + +inst_11: +// rs2==x8, +// opcode:c.sdspz; op1:x2; op2:x8; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x9 +TEST_STORE_ZILSD(x1,x3,0,x2,x8,x9,-0x80000000,-0x80000000,0x0,22*XLEN/8,c.sdsp,0) + +inst_12: +// rs2==x6, +// opcode:c.sdspz; op1:x2; op2:x6; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x7 +TEST_STORE_ZILSD(x1,x3,0,x2,x6,x7,-0x80000000,-0x80000000,0x0,24*XLEN/8,c.sdsp,0) + +inst_13: +// rs2==x4, +// opcode:c.sdspz; op1:x2; op2:x4; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x5 +TEST_STORE_ZILSD(x1,x3,0,x2,x4,x5,-0x80000000,-0x80000000,0x0,26*XLEN/8,c.sdsp,0) +RVTEST_SIGBASE(x4,signature_x4_0) + +inst_14: +// rs2==x2, +// opcode:c.sdspz; op1:x2; op2:x2; op2val:-0x80000000; op3val:-0x80000000; immval:0x0; rs2_hi:x3 +TEST_STORE_ZILSD(x4,x3,0,x2,x2,x3,-0x80000000,-0x80000000,0x0,0*XLEN/8,c.sdsp,0) + +inst_15: +// rs2==x0, +// opcode:c.sdspz; op1:x2; op2:x0; op2val:0x0; op3val:-0x80000000; immval:0x0; rs2_hi:x1 +TEST_STORE_ZILSD(x4,x3,0,x2,x0,x1,0x0,-0x80000000,0x0,2*XLEN/8,c.sdsp,0) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((XLEN/8)/4),4,0xdeadbeef + + +signature_x4_0: + .fill 4*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zilsd/src/ld-01.S b/riscv-test-suite/rv32i_m/Zilsd/src/ld-01.S new file mode 100644 index 0000000000..b7b74e6a1f --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zilsd/src/ld-01.S @@ -0,0 +1,246 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Mar 25 08:20:56 2025 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/zilsd/rv32zilsd.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the ldz instruction of the RISC-V RV32Zilsd extension for the ld covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IZilsd") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zilsd.*);def TEST_CASE_1=True;",ld) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 == rd, rs1==x30, rd==x30, imm_val > 0, ea_align == 0 and (imm_val % 8) == 5 +// opcode:$opcode op1:x30; dest:x30; immval:0x555; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x1,x2,0,x30,x30,x31,0x555,0*XLEN/8,ld,0) + +inst_1: +// rs1 != rd, rs1==x31, rd==x28, imm_val == 0, ea_align == 0 and (imm_val % 8) == 0 +// opcode:$opcode op1:x31; dest:x28; immval:0x0; align:0;rd_hi:x29 +TEST_LOAD_ZILSD(x1,x2,0,x31,x28,x29,0x0,2*XLEN/8,ld,0) + +inst_2: +// rs1==x29, rd==x26, imm_val < 0, ea_align == 0 and (imm_val % 8) == 2 +// opcode:$opcode op1:x29; dest:x26; immval:-0x556; align:0;rd_hi:x27 +TEST_LOAD_ZILSD(x1,x2,0,x29,x26,x27,-0x556,4*XLEN/8,ld,0) + +inst_3: +// rs1==x28, rd==x24, ea_align == 0 and (imm_val % 8) == 7, +// opcode:$opcode op1:x28; dest:x24; immval:-0x401; align:0;rd_hi:x25 +TEST_LOAD_ZILSD(x1,x2,0,x28,x24,x25,-0x401,6*XLEN/8,ld,0) + +inst_4: +// rs1==x27, rd==x22, ea_align == 0 and (imm_val % 8) == 6, +// opcode:$opcode op1:x27; dest:x22; immval:0x6; align:0;rd_hi:x23 +TEST_LOAD_ZILSD(x1,x2,0,x27,x22,x23,0x6,8*XLEN/8,ld,0) + +inst_5: +// rs1==x26, rd==x20, ea_align == 0 and (imm_val % 8) == 4, +// opcode:$opcode op1:x26; dest:x20; immval:0x4; align:0;rd_hi:x21 +TEST_LOAD_ZILSD(x1,x2,0,x26,x20,x21,0x4,10*XLEN/8,ld,0) + +inst_6: +// rs1==x25, rd==x18, ea_align == 0 and (imm_val % 8) == 3, +// opcode:$opcode op1:x25; dest:x18; immval:0x3; align:0;rd_hi:x19 +TEST_LOAD_ZILSD(x1,x2,0,x25,x18,x19,0x3,12*XLEN/8,ld,0) + +inst_7: +// rs1==x24, rd==x16, ea_align == 0 and (imm_val % 8) == 1, +// opcode:$opcode op1:x24; dest:x16; immval:0x9; align:0;rd_hi:x17 +TEST_LOAD_ZILSD(x1,x2,0,x24,x16,x17,0x9,14*XLEN/8,ld,0) + +inst_8: +// rs1==x23, rd==x14, +// opcode:$opcode op1:x23; dest:x14; immval:-0x800; align:0;rd_hi:x15 +TEST_LOAD_ZILSD(x1,x2,0,x23,x14,x15,-0x800,16*XLEN/8,ld,0) + +inst_9: +// rs1==x22, rd==x12, +// opcode:$opcode op1:x22; dest:x12; immval:-0x800; align:0;rd_hi:x13 +TEST_LOAD_ZILSD(x1,x2,0,x22,x12,x13,-0x800,18*XLEN/8,ld,0) + +inst_10: +// rs1==x21, rd==x10, +// opcode:$opcode op1:x21; dest:x10; immval:-0x800; align:0;rd_hi:x11 +TEST_LOAD_ZILSD(x1,x2,0,x21,x10,x11,-0x800,20*XLEN/8,ld,0) + +inst_11: +// rs1==x20, rd==x8, +// opcode:$opcode op1:x20; dest:x8; immval:-0x800; align:0;rd_hi:x9 +TEST_LOAD_ZILSD(x1,x2,0,x20,x8,x9,-0x800,22*XLEN/8,ld,0) + +inst_12: +// rs1==x19, rd==x6, +// opcode:$opcode op1:x19; dest:x6; immval:-0x800; align:0;rd_hi:x7 +TEST_LOAD_ZILSD(x1,x2,0,x19,x6,x7,-0x800,24*XLEN/8,ld,0) + +inst_13: +// rs1==x18, rd==x4, +// opcode:$opcode op1:x18; dest:x4; immval:-0x800; align:0;rd_hi:x5 +TEST_LOAD_ZILSD(x1,x19,0,x18,x4,x5,-0x800,26*XLEN/8,ld,0) +RVTEST_SIGBASE(x18,signature_x18_0) + +inst_14: +// rs1==x17, rd==x2, +// opcode:$opcode op1:x17; dest:x2; immval:-0x800; align:0;rd_hi:x3 +TEST_LOAD_ZILSD(x18,x19,0,x17,x2,x3,-0x800,0*XLEN/8,ld,0) + +inst_15: +// rs1==x16, rd==x0, +// opcode:$opcode op1:x16; dest:x0; immval:-0x800; align:0;rd_hi:x1 +TEST_LOAD_ZILSD(x18,x19,0,x16,x0,x1,-0x800,2*XLEN/8,ld,0) + +inst_16: +// rs1==x15, +// opcode:$opcode op1:x15; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x15,x30,x31,-0x800,4*XLEN/8,ld,0) + +inst_17: +// rs1==x14, +// opcode:$opcode op1:x14; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x14,x30,x31,-0x800,6*XLEN/8,ld,0) + +inst_18: +// rs1==x13, +// opcode:$opcode op1:x13; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x13,x30,x31,-0x800,8*XLEN/8,ld,0) + +inst_19: +// rs1==x12, +// opcode:$opcode op1:x12; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x12,x30,x31,-0x800,10*XLEN/8,ld,0) + +inst_20: +// rs1==x11, +// opcode:$opcode op1:x11; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x11,x30,x31,-0x800,12*XLEN/8,ld,0) + +inst_21: +// rs1==x10, +// opcode:$opcode op1:x10; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x10,x30,x31,-0x800,14*XLEN/8,ld,0) + +inst_22: +// rs1==x9, +// opcode:$opcode op1:x9; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x9,x30,x31,-0x800,16*XLEN/8,ld,0) + +inst_23: +// rs1==x8, +// opcode:$opcode op1:x8; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x8,x30,x31,-0x800,18*XLEN/8,ld,0) + +inst_24: +// rs1==x7, +// opcode:$opcode op1:x7; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x7,x30,x31,-0x800,20*XLEN/8,ld,0) + +inst_25: +// rs1==x6, +// opcode:$opcode op1:x6; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x6,x30,x31,-0x800,22*XLEN/8,ld,0) + +inst_26: +// rs1==x5, +// opcode:$opcode op1:x5; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x5,x30,x31,-0x800,24*XLEN/8,ld,0) + +inst_27: +// rs1==x4, +// opcode:$opcode op1:x4; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x4,x30,x31,-0x800,26*XLEN/8,ld,0) + +inst_28: +// rs1==x3, +// opcode:$opcode op1:x3; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x3,x30,x31,-0x800,28*XLEN/8,ld,0) + +inst_29: +// rs1==x2, +// opcode:$opcode op1:x2; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x2,x30,x31,-0x800,30*XLEN/8,ld,0) + +inst_30: +// rs1==x1, +// opcode:$opcode op1:x1; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x1,x30,x31,-0x800,32*XLEN/8,ld,0) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((XLEN/8)/4),4,0xdeadbeef + + +signature_x18_0: + .fill 34*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zilsd/src/sd-01.S b/riscv-test-suite/rv32i_m/Zilsd/src/sd-01.S new file mode 100644 index 0000000000..b16ae84e9f --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zilsd/src/sd-01.S @@ -0,0 +1,246 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Mar 25 08:20:56 2025 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/zilsd/rv32zilsd.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the sdz instruction of the RISC-V RV32Zilsd extension for the sd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IZilsd") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zilsd.*);def TEST_CASE_1=True;",sd) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1 != rs2, rs1==x31, rs2==x30, rs2_val == 1, ea_align == 0 and (imm_val % 8) == 0, imm_val < 0 +// opcode:$opcode; op1:x29; op2:x30; op2val:0x1;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x1,x2,0,x29,x30,x31,0x1,-0x80000000,-0x800,0*XLEN/8,sd,0) + +inst_1: +// rs1==x30, rs2==x28, rs2_val == 0, +// opcode:$opcode; op1:x30; op2:x28; op2val:0x0;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x29 +TEST_STORE_ZILSD(x1,x2,0,x30,x28,x29,0x0,-0x80000000,-0x800,2*XLEN/8,sd,0) + +inst_2: +// rs1==x29, rs2==x26, rs2_val == (2**(xlen-1)-1), +// opcode:$opcode; op1:x29; op2:x26; op2val:0x7fffffff;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x27 +TEST_STORE_ZILSD(x1,x2,0,x29,x26,x27,0x7fffffff,-0x80000000,-0x800,4*XLEN/8,sd,0) + +inst_3: +// rs1==x28, rs2==x24, rs2_val == (-2**(xlen-1)), +// opcode:$opcode; op1:x28; op2:x24; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x25 +TEST_STORE_ZILSD(x1,x2,0,x28,x24,x25,-0x80000000,-0x80000000,-0x800,6*XLEN/8,sd,0) + +inst_4: +// rs1==x27, rs2==x22, imm_val > 0, ea_align == 0 and (imm_val % 8) == 5 +// opcode:$opcode; op1:x27; op2:x22; op2val:-0x80000000;op3val:-0x80000000; immval:0x555; align:0; rs2_hi:x23 +TEST_STORE_ZILSD(x1,x2,0,x27,x22,x23,-0x80000000,-0x80000000,0x555,8*XLEN/8,sd,0) + +inst_5: +// rs1==x26, rs2==x20, imm_val == 0, +// opcode:$opcode; op1:x26; op2:x20; op2val:-0x80000000;op3val:-0x80000000; immval:0x0; align:0; rs2_hi:x21 +TEST_STORE_ZILSD(x1,x2,0,x26,x20,x21,-0x80000000,-0x80000000,0x0,10*XLEN/8,sd,0) + +inst_6: +// rs1==x25, rs2==x18, ea_align == 0 and (imm_val % 8) == 7, +// opcode:$opcode; op1:x25; op2:x18; op2val:-0x80000000;op3val:-0x80000000; immval:-0x401; align:0; rs2_hi:x19 +TEST_STORE_ZILSD(x1,x2,0,x25,x18,x19,-0x80000000,-0x80000000,-0x401,12*XLEN/8,sd,0) + +inst_7: +// rs1==x24, rs2==x16, ea_align == 0 and (imm_val % 8) == 6, +// opcode:$opcode; op1:x24; op2:x16; op2val:-0x80000000;op3val:-0x80000000; immval:0x6; align:0; rs2_hi:x17 +TEST_STORE_ZILSD(x1,x2,0,x24,x16,x17,-0x80000000,-0x80000000,0x6,14*XLEN/8,sd,0) + +inst_8: +// rs1==x23, rs2==x14, ea_align == 0 and (imm_val % 8) == 4, +// opcode:$opcode; op1:x23; op2:x14; op2val:-0x80000000;op3val:-0x80000000; immval:0x4; align:0; rs2_hi:x15 +TEST_STORE_ZILSD(x1,x2,0,x23,x14,x15,-0x80000000,-0x80000000,0x4,16*XLEN/8,sd,0) + +inst_9: +// rs1==x22, rs2==x12, ea_align == 0 and (imm_val % 8) == 3, +// opcode:$opcode; op1:x22; op2:x12; op2val:-0x80000000;op3val:-0x80000000; immval:0x3; align:0; rs2_hi:x13 +TEST_STORE_ZILSD(x1,x2,0,x22,x12,x13,-0x80000000,-0x80000000,0x3,18*XLEN/8,sd,0) + +inst_10: +// rs1==x21, rs2==x10, ea_align == 0 and (imm_val % 8) == 2, +// opcode:$opcode; op1:x21; op2:x10; op2val:-0x80000000;op3val:-0x80000000; immval:-0x556; align:0; rs2_hi:x11 +TEST_STORE_ZILSD(x1,x2,0,x21,x10,x11,-0x80000000,-0x80000000,-0x556,20*XLEN/8,sd,0) + +inst_11: +// rs1==x20, rs2==x8, ea_align == 0 and (imm_val % 8) == 1, +// opcode:$opcode; op1:x20; op2:x8; op2val:-0x80000000;op3val:-0x80000000; immval:0x9; align:0; rs2_hi:x9 +TEST_STORE_ZILSD(x1,x2,0,x20,x8,x9,-0x80000000,-0x80000000,0x9,22*XLEN/8,sd,0) + +inst_12: +// rs1==x19, rs2==x6, +// opcode:$opcode; op1:x19; op2:x6; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x7 +TEST_STORE_ZILSD(x1,x2,0,x19,x6,x7,-0x80000000,-0x80000000,-0x800,24*XLEN/8,sd,0) + +inst_13: +// rs1==x18, rs2==x4, +// opcode:$opcode; op1:x18; op2:x4; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x5 +TEST_STORE_ZILSD(x1,x19,0,x18,x4,x5,-0x80000000,-0x80000000,-0x800,26*XLEN/8,sd,0) +RVTEST_SIGBASE(x18,signature_x18_0) + +inst_14: +// rs1==x17, rs2==x2, +// opcode:$opcode; op1:x17; op2:x2; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x3 +TEST_STORE_ZILSD(x18,x19,0,x17,x2,x3,-0x80000000,-0x80000000,-0x800,0*XLEN/8,sd,0) + +inst_15: +// rs1==x16, rs2==x0, +// opcode:$opcode; op1:x16; op2:x0; op2val:0x0;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x1 +TEST_STORE_ZILSD(x18,x19,0,x16,x0,x1,0x0,-0x80000000,-0x800,2*XLEN/8,sd,0) + +inst_16: +// rs1==x15, +// opcode:$opcode; op1:x15; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x15,x30,x31,-0x80000000,-0x80000000,-0x800,4*XLEN/8,sd,0) + +inst_17: +// rs1==x14, +// opcode:$opcode; op1:x14; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x14,x30,x31,-0x80000000,-0x80000000,-0x800,6*XLEN/8,sd,0) + +inst_18: +// rs1==x13, +// opcode:$opcode; op1:x13; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x13,x30,x31,-0x80000000,-0x80000000,-0x800,8*XLEN/8,sd,0) + +inst_19: +// rs1==x12, +// opcode:$opcode; op1:x12; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x12,x30,x31,-0x80000000,-0x80000000,-0x800,10*XLEN/8,sd,0) + +inst_20: +// rs1==x11, +// opcode:$opcode; op1:x11; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x11,x30,x31,-0x80000000,-0x80000000,-0x800,12*XLEN/8,sd,0) + +inst_21: +// rs1==x10, +// opcode:$opcode; op1:x10; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x10,x30,x31,-0x80000000,-0x80000000,-0x800,14*XLEN/8,sd,0) + +inst_22: +// rs1==x9, +// opcode:$opcode; op1:x9; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x9,x30,x31,-0x80000000,-0x80000000,-0x800,16*XLEN/8,sd,0) + +inst_23: +// rs1==x8, +// opcode:$opcode; op1:x8; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x8,x30,x31,-0x80000000,-0x80000000,-0x800,18*XLEN/8,sd,0) + +inst_24: +// rs1==x7, +// opcode:$opcode; op1:x7; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x7,x30,x31,-0x80000000,-0x80000000,-0x800,20*XLEN/8,sd,0) + +inst_25: +// rs1==x6, +// opcode:$opcode; op1:x6; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x6,x30,x31,-0x80000000,-0x80000000,-0x800,22*XLEN/8,sd,0) + +inst_26: +// rs1==x5, +// opcode:$opcode; op1:x5; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x5,x30,x31,-0x80000000,-0x80000000,-0x800,24*XLEN/8,sd,0) + +inst_27: +// rs1==x4, +// opcode:$opcode; op1:x4; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x4,x30,x31,-0x80000000,-0x80000000,-0x800,26*XLEN/8,sd,0) + +inst_28: +// rs1==x3, +// opcode:$opcode; op1:x3; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x3,x30,x31,-0x80000000,-0x80000000,-0x800,28*XLEN/8,sd,0) + +inst_29: +// rs1==x2, +// opcode:$opcode; op1:x2; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x2,x30,x31,-0x80000000,-0x80000000,-0x800,30*XLEN/8,sd,0) + +inst_30: +// rs1==x1, +// opcode:$opcode; op1:x1; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x1,x30,x31,-0x80000000,-0x80000000,-0x800,32*XLEN/8,sd,0) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((XLEN/8)/4),4,0xdeadbeef + + +signature_x18_0: + .fill 34*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-ld-01.S b/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-ld-01.S new file mode 100644 index 0000000000..46c508a03d --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-ld-01.S @@ -0,0 +1,248 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Apr 8 11:18:48 2025 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/zilsd/rv32zilsd_priv.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the ldz instruction of the RISC-V RV32Zilsd extension for the misalign-ld covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IZicsr_Zilsd") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True;def TEST_CASE_1=True;",misalign-ld) + +RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-ld) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1==x31, rd==x30, ea_align == 7, +// opcode:$opcode op1:x31; dest:x30; immval:-0x800; align:7;rd_hi:x31 +TEST_LOAD_ZILSD(x1,x2,0,x31,x30,x31,-0x800,0*XLEN/8,ld,7) + +inst_1: +// rs1==x30, rd==x28, ea_align == 6, +// opcode:$opcode op1:x30; dest:x28; immval:-0x800; align:6;rd_hi:x29 +TEST_LOAD_ZILSD(x1,x2,0,x30,x28,x29,-0x800,2*XLEN/8,ld,6) + +inst_2: +// rs1==x29, rd==x26, ea_align == 5, +// opcode:$opcode op1:x29; dest:x26; immval:-0x800; align:5;rd_hi:x27 +TEST_LOAD_ZILSD(x1,x2,0,x29,x26,x27,-0x800,4*XLEN/8,ld,5) + +inst_3: +// rs1==x28, rd==x24, ea_align == 4, +// opcode:$opcode op1:x28; dest:x24; immval:-0x800; align:4;rd_hi:x25 +TEST_LOAD_ZILSD(x1,x2,0,x28,x24,x25,-0x800,6*XLEN/8,ld,4) + +inst_4: +// rs1==x27, rd==x22, ea_align == 3, +// opcode:$opcode op1:x27; dest:x22; immval:-0x800; align:3;rd_hi:x23 +TEST_LOAD_ZILSD(x1,x2,0,x27,x22,x23,-0x800,8*XLEN/8,ld,3) + +inst_5: +// rs1==x26, rd==x20, ea_align == 2, +// opcode:$opcode op1:x26; dest:x20; immval:-0x800; align:2;rd_hi:x21 +TEST_LOAD_ZILSD(x1,x2,0,x26,x20,x21,-0x800,10*XLEN/8,ld,2) + +inst_6: +// rs1==x25, rd==x18, ea_align == 1, +// opcode:$opcode op1:x25; dest:x18; immval:-0x800; align:1;rd_hi:x19 +TEST_LOAD_ZILSD(x1,x2,0,x25,x18,x19,-0x800,12*XLEN/8,ld,1) + +inst_7: +// rs1==x24, rd==x16, +// opcode:$opcode op1:x24; dest:x16; immval:-0x800; align:0;rd_hi:x17 +TEST_LOAD_ZILSD(x1,x2,0,x24,x16,x17,-0x800,14*XLEN/8,ld,0) + +inst_8: +// rs1==x23, rd==x14, +// opcode:$opcode op1:x23; dest:x14; immval:-0x800; align:0;rd_hi:x15 +TEST_LOAD_ZILSD(x1,x2,0,x23,x14,x15,-0x800,16*XLEN/8,ld,0) + +inst_9: +// rs1==x22, rd==x12, +// opcode:$opcode op1:x22; dest:x12; immval:-0x800; align:0;rd_hi:x13 +TEST_LOAD_ZILSD(x1,x2,0,x22,x12,x13,-0x800,18*XLEN/8,ld,0) + +inst_10: +// rs1==x21, rd==x10, +// opcode:$opcode op1:x21; dest:x10; immval:-0x800; align:0;rd_hi:x11 +TEST_LOAD_ZILSD(x1,x2,0,x21,x10,x11,-0x800,20*XLEN/8,ld,0) + +inst_11: +// rs1==x20, rd==x8, +// opcode:$opcode op1:x20; dest:x8; immval:-0x800; align:0;rd_hi:x9 +TEST_LOAD_ZILSD(x1,x2,0,x20,x8,x9,-0x800,22*XLEN/8,ld,0) + +inst_12: +// rs1==x19, rd==x6, +// opcode:$opcode op1:x19; dest:x6; immval:-0x800; align:0;rd_hi:x7 +TEST_LOAD_ZILSD(x1,x2,0,x19,x6,x7,-0x800,24*XLEN/8,ld,0) + +inst_13: +// rs1==x18, rd==x4, +// opcode:$opcode op1:x18; dest:x4; immval:-0x800; align:0;rd_hi:x5 +TEST_LOAD_ZILSD(x1,x19,0,x18,x4,x5,-0x800,26*XLEN/8,ld,0) +RVTEST_SIGBASE(x18,signature_x18_0) + +inst_14: +// rs1==x17, rd==x2, +// opcode:$opcode op1:x17; dest:x2; immval:-0x800; align:0;rd_hi:x3 +TEST_LOAD_ZILSD(x18,x19,0,x17,x2,x3,-0x800,0*XLEN/8,ld,0) + +inst_15: +// rs1==x16, rd==x0, +// opcode:$opcode op1:x16; dest:x0; immval:-0x800; align:0;rd_hi:x1 +TEST_LOAD_ZILSD(x18,x19,0,x16,x0,x1,-0x800,2*XLEN/8,ld,0) + +inst_16: +// rs1==x15, +// opcode:$opcode op1:x15; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x15,x30,x31,-0x800,4*XLEN/8,ld,0) + +inst_17: +// rs1==x14, +// opcode:$opcode op1:x14; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x14,x30,x31,-0x800,6*XLEN/8,ld,0) + +inst_18: +// rs1==x13, +// opcode:$opcode op1:x13; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x13,x30,x31,-0x800,8*XLEN/8,ld,0) + +inst_19: +// rs1==x12, +// opcode:$opcode op1:x12; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x12,x30,x31,-0x800,10*XLEN/8,ld,0) + +inst_20: +// rs1==x11, +// opcode:$opcode op1:x11; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x11,x30,x31,-0x800,12*XLEN/8,ld,0) + +inst_21: +// rs1==x10, +// opcode:$opcode op1:x10; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x10,x30,x31,-0x800,14*XLEN/8,ld,0) + +inst_22: +// rs1==x9, +// opcode:$opcode op1:x9; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x9,x30,x31,-0x800,16*XLEN/8,ld,0) + +inst_23: +// rs1==x8, +// opcode:$opcode op1:x8; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x8,x30,x31,-0x800,18*XLEN/8,ld,0) + +inst_24: +// rs1==x7, +// opcode:$opcode op1:x7; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x7,x30,x31,-0x800,20*XLEN/8,ld,0) + +inst_25: +// rs1==x6, +// opcode:$opcode op1:x6; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x6,x30,x31,-0x800,22*XLEN/8,ld,0) + +inst_26: +// rs1==x5, +// opcode:$opcode op1:x5; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x5,x30,x31,-0x800,24*XLEN/8,ld,0) + +inst_27: +// rs1==x4, +// opcode:$opcode op1:x4; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x4,x30,x31,-0x800,26*XLEN/8,ld,0) + +inst_28: +// rs1==x3, +// opcode:$opcode op1:x3; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x3,x30,x31,-0x800,28*XLEN/8,ld,0) + +inst_29: +// rs1==x2, +// opcode:$opcode op1:x2; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x2,x30,x31,-0x800,30*XLEN/8,ld,0) + +inst_30: +// rs1==x1, +// opcode:$opcode op1:x1; dest:x30; immval:-0x800; align:0;rd_hi:x31 +TEST_LOAD_ZILSD(x18,x19,0,x1,x30,x31,-0x800,32*XLEN/8,ld,0) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((XLEN/8)/4),4,0xdeadbeef + + +signature_x18_0: + .fill 34*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-sd-01.S b/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-sd-01.S new file mode 100644 index 0000000000..c0a45e4279 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zilsd_privilege/src/misalign-sd-01.S @@ -0,0 +1,248 @@ + +// ----------- +// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg) +// version : 0.12.2 +// timestamp : Tue Apr 8 11:18:48 2025 GMT +// usage : riscv_ctg \ +// -- cgf // --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/dataset.cgf \ +// --cgf /home/trdthg/repo/act/riscv-arch-test/coverage/zilsd/rv32zilsd_priv.cgf \ + \ +// -- xlen 32 \ +// ----------- +// +// ----------- +// Copyright (c) 2020. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// +// This assembly file tests the sdz instruction of the RISC-V RV32Zilsd extension for the misalign-sd covergroup. +// +#include "model_test.h" +#include "arch_test.h" +RVTEST_ISA("RV32IZicsr_Zilsd") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*Zilsd.*); check hw_data_misaligned_support:=True;def TEST_CASE_1=True;",misalign-sd) + +RVTEST_CASE(1,"//check ISA:=regex(.*I.*Zicsr.*Zilsd.); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-sd) + +RVTEST_SIGBASE(x1,signature_x1_1) + +inst_0: +// rs1==x31, rs2==x30, ea_align == 7, +// opcode:$opcode; op1:x29; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:7; rs2_hi:x31 +TEST_STORE_ZILSD(x1,x2,0,x29,x30,x31,-0x80000000,-0x80000000,-0x800,0*XLEN/8,sd,7) + +inst_1: +// rs1==x30, rs2==x28, ea_align == 6, +// opcode:$opcode; op1:x30; op2:x28; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:6; rs2_hi:x29 +TEST_STORE_ZILSD(x1,x2,0,x30,x28,x29,-0x80000000,-0x80000000,-0x800,2*XLEN/8,sd,6) + +inst_2: +// rs1==x29, rs2==x26, ea_align == 5, +// opcode:$opcode; op1:x29; op2:x26; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:5; rs2_hi:x27 +TEST_STORE_ZILSD(x1,x2,0,x29,x26,x27,-0x80000000,-0x80000000,-0x800,4*XLEN/8,sd,5) + +inst_3: +// rs1==x28, rs2==x24, ea_align == 4, +// opcode:$opcode; op1:x28; op2:x24; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:4; rs2_hi:x25 +TEST_STORE_ZILSD(x1,x2,0,x28,x24,x25,-0x80000000,-0x80000000,-0x800,6*XLEN/8,sd,4) + +inst_4: +// rs1==x27, rs2==x22, ea_align == 3, +// opcode:$opcode; op1:x27; op2:x22; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:3; rs2_hi:x23 +TEST_STORE_ZILSD(x1,x2,0,x27,x22,x23,-0x80000000,-0x80000000,-0x800,8*XLEN/8,sd,3) + +inst_5: +// rs1==x26, rs2==x20, ea_align == 2, +// opcode:$opcode; op1:x26; op2:x20; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:2; rs2_hi:x21 +TEST_STORE_ZILSD(x1,x2,0,x26,x20,x21,-0x80000000,-0x80000000,-0x800,10*XLEN/8,sd,2) + +inst_6: +// rs1==x25, rs2==x18, ea_align == 1, +// opcode:$opcode; op1:x25; op2:x18; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:1; rs2_hi:x19 +TEST_STORE_ZILSD(x1,x2,0,x25,x18,x19,-0x80000000,-0x80000000,-0x800,12*XLEN/8,sd,1) + +inst_7: +// rs1==x24, rs2==x16, +// opcode:$opcode; op1:x24; op2:x16; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x17 +TEST_STORE_ZILSD(x1,x2,0,x24,x16,x17,-0x80000000,-0x80000000,-0x800,14*XLEN/8,sd,0) + +inst_8: +// rs1==x23, rs2==x14, +// opcode:$opcode; op1:x23; op2:x14; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x15 +TEST_STORE_ZILSD(x1,x2,0,x23,x14,x15,-0x80000000,-0x80000000,-0x800,16*XLEN/8,sd,0) + +inst_9: +// rs1==x22, rs2==x12, +// opcode:$opcode; op1:x22; op2:x12; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x13 +TEST_STORE_ZILSD(x1,x2,0,x22,x12,x13,-0x80000000,-0x80000000,-0x800,18*XLEN/8,sd,0) + +inst_10: +// rs1==x21, rs2==x10, +// opcode:$opcode; op1:x21; op2:x10; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x11 +TEST_STORE_ZILSD(x1,x2,0,x21,x10,x11,-0x80000000,-0x80000000,-0x800,20*XLEN/8,sd,0) + +inst_11: +// rs1==x20, rs2==x8, +// opcode:$opcode; op1:x20; op2:x8; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x9 +TEST_STORE_ZILSD(x1,x2,0,x20,x8,x9,-0x80000000,-0x80000000,-0x800,22*XLEN/8,sd,0) + +inst_12: +// rs1==x19, rs2==x6, +// opcode:$opcode; op1:x19; op2:x6; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x7 +TEST_STORE_ZILSD(x1,x2,0,x19,x6,x7,-0x80000000,-0x80000000,-0x800,24*XLEN/8,sd,0) + +inst_13: +// rs1==x18, rs2==x4, +// opcode:$opcode; op1:x18; op2:x4; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x5 +TEST_STORE_ZILSD(x1,x19,0,x18,x4,x5,-0x80000000,-0x80000000,-0x800,26*XLEN/8,sd,0) +RVTEST_SIGBASE(x18,signature_x18_0) + +inst_14: +// rs1==x17, rs2==x2, +// opcode:$opcode; op1:x17; op2:x2; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x3 +TEST_STORE_ZILSD(x18,x19,0,x17,x2,x3,-0x80000000,-0x80000000,-0x800,0*XLEN/8,sd,0) + +inst_15: +// rs1==x16, rs2==x0, +// opcode:$opcode; op1:x16; op2:x0; op2val:0x0;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x1 +TEST_STORE_ZILSD(x18,x19,0,x16,x0,x1,0x0,-0x80000000,-0x800,2*XLEN/8,sd,0) + +inst_16: +// rs1==x15, +// opcode:$opcode; op1:x15; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x15,x30,x31,-0x80000000,-0x80000000,-0x800,4*XLEN/8,sd,0) + +inst_17: +// rs1==x14, +// opcode:$opcode; op1:x14; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x14,x30,x31,-0x80000000,-0x80000000,-0x800,6*XLEN/8,sd,0) + +inst_18: +// rs1==x13, +// opcode:$opcode; op1:x13; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x13,x30,x31,-0x80000000,-0x80000000,-0x800,8*XLEN/8,sd,0) + +inst_19: +// rs1==x12, +// opcode:$opcode; op1:x12; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x12,x30,x31,-0x80000000,-0x80000000,-0x800,10*XLEN/8,sd,0) + +inst_20: +// rs1==x11, +// opcode:$opcode; op1:x11; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x11,x30,x31,-0x80000000,-0x80000000,-0x800,12*XLEN/8,sd,0) + +inst_21: +// rs1==x10, +// opcode:$opcode; op1:x10; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x10,x30,x31,-0x80000000,-0x80000000,-0x800,14*XLEN/8,sd,0) + +inst_22: +// rs1==x9, +// opcode:$opcode; op1:x9; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x9,x30,x31,-0x80000000,-0x80000000,-0x800,16*XLEN/8,sd,0) + +inst_23: +// rs1==x8, +// opcode:$opcode; op1:x8; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x8,x30,x31,-0x80000000,-0x80000000,-0x800,18*XLEN/8,sd,0) + +inst_24: +// rs1==x7, +// opcode:$opcode; op1:x7; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x7,x30,x31,-0x80000000,-0x80000000,-0x800,20*XLEN/8,sd,0) + +inst_25: +// rs1==x6, +// opcode:$opcode; op1:x6; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x6,x30,x31,-0x80000000,-0x80000000,-0x800,22*XLEN/8,sd,0) + +inst_26: +// rs1==x5, +// opcode:$opcode; op1:x5; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x5,x30,x31,-0x80000000,-0x80000000,-0x800,24*XLEN/8,sd,0) + +inst_27: +// rs1==x4, +// opcode:$opcode; op1:x4; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x4,x30,x31,-0x80000000,-0x80000000,-0x800,26*XLEN/8,sd,0) + +inst_28: +// rs1==x3, +// opcode:$opcode; op1:x3; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x3,x30,x31,-0x80000000,-0x80000000,-0x800,28*XLEN/8,sd,0) + +inst_29: +// rs1==x2, +// opcode:$opcode; op1:x2; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x2,x30,x31,-0x80000000,-0x80000000,-0x800,30*XLEN/8,sd,0) + +inst_30: +// rs1==x1, +// opcode:$opcode; op1:x1; op2:x30; op2val:-0x80000000;op3val:-0x80000000; immval:-0x800; align:0; rs2_hi:x31 +TEST_STORE_ZILSD(x18,x19,0,x1,x30,x31,-0x80000000,-0x80000000,-0x800,32*XLEN/8,sd,0) +#endif + + +RVTEST_CODE_END +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.align 4 +rvtest_data: +.word 0xbabecafe +.word 0xabecafeb +.word 0xbecafeba +.word 0xecafebab +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + + + +signature_x1_0: + .fill 0*((XLEN/8)/4),4,0xdeadbeef + + +signature_x1_1: + .fill 28*((XLEN/8)/4),4,0xdeadbeef + + +signature_x18_0: + .fill 34*((XLEN/8)/4),4,0xdeadbeef + +#ifdef rvtest_mtrap_routine +tsig_begin_canary: +CANARY; + +mtrap_sigptr: + .fill 64*XLEN/32,4,0xdeadbeef + +tsig_end_canary: +CANARY; +#endif + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif + + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END