diff --git a/librz/arch/isa/mips/mips_il.c b/librz/arch/isa/mips/mips_il.c new file mode 100644 index 00000000000..e26194cb4c8 --- /dev/null +++ b/librz/arch/isa/mips/mips_il.c @@ -0,0 +1,1376 @@ +// SPDX-FileCopyrightText: 2025 deroad +// SPDX-License-Identifier: LGPL-3.0-only + +#include "mips_internal.h" + +RZ_IPI RzILOpEffect *mips_il(RZ_NONNULL cs_insn *insn) { + rz_return_val_if_fail(insn, NULL); + + switch (insn->id) { + case MIPS_INS_ABS: + case MIPS_INS_ALIGN: + case MIPS_INS_BEQL: + case MIPS_INS_BGE: + case MIPS_INS_BGEL: + case MIPS_INS_BGEU: + case MIPS_INS_BGEUL: + case MIPS_INS_BGT: + case MIPS_INS_BGTL: + case MIPS_INS_BGTU: + case MIPS_INS_BGTUL: + case MIPS_INS_BLE: + case MIPS_INS_BLEL: + case MIPS_INS_BLEU: + case MIPS_INS_BLEUL: + case MIPS_INS_BLT: + case MIPS_INS_BLTL: + case MIPS_INS_BLTU: + case MIPS_INS_BLTUL: + case MIPS_INS_BNEL: + case MIPS_INS_B: + case MIPS_INS_BEQ: + case MIPS_INS_BNE: + case MIPS_INS_CFTC1: + case MIPS_INS_CTTC1: + case MIPS_INS_DMUL: + case MIPS_INS_DMULO: + case MIPS_INS_DMULOU: + case MIPS_INS_DROL: + case MIPS_INS_DROR: + case MIPS_INS_DDIV: + case MIPS_INS_DREM: + case MIPS_INS_DDIVU: + case MIPS_INS_DREMU: + case MIPS_INS_JAL: + case MIPS_INS_LD: + case MIPS_INS_LWM: + case MIPS_INS_LA: + case MIPS_INS_DLA: + case MIPS_INS_LI: + case MIPS_INS_DLI: + case MIPS_INS_LI_D: + case MIPS_INS_LI_S: + case MIPS_INS_MFTACX: + case MIPS_INS_MFTC0: + case MIPS_INS_MFTC1: + case MIPS_INS_MFTDSP: + case MIPS_INS_MFTGPR: + case MIPS_INS_MFTHC1: + case MIPS_INS_MFTHI: + case MIPS_INS_MFTLO: + case MIPS_INS_MTTACX: + case MIPS_INS_MTTC0: + case MIPS_INS_MTTC1: + case MIPS_INS_MTTDSP: + case MIPS_INS_MTTGPR: + case MIPS_INS_MTTHC1: + case MIPS_INS_MTTHI: + case MIPS_INS_MTTLO: + case MIPS_INS_MUL: + case MIPS_INS_MULO: + case MIPS_INS_MULOU: + case MIPS_INS_NOR: + case MIPS_INS_ADDIU: + case MIPS_INS_ANDI: + case MIPS_INS_SUBU: + case MIPS_INS_TRUNC_W_D: + case MIPS_INS_TRUNC_W_S: + case MIPS_INS_ROL: + case MIPS_INS_ROR: + case MIPS_INS_S_D: + case MIPS_INS_SD: + case MIPS_INS_DIV: + case MIPS_INS_SEQ: + case MIPS_INS_SGE: + case MIPS_INS_SGEU: + case MIPS_INS_SGT: + case MIPS_INS_SGTU: + case MIPS_INS_SLE: + case MIPS_INS_SLEU: + case MIPS_INS_SLT: + case MIPS_INS_SLTU: + case MIPS_INS_SNE: + case MIPS_INS_REM: + case MIPS_INS_SWM: + case MIPS_INS_SAA: + case MIPS_INS_SAAD: + case MIPS_INS_DIVU: + case MIPS_INS_REMU: + case MIPS_INS_ULH: + case MIPS_INS_ULHU: + case MIPS_INS_ULW: + case MIPS_INS_USH: + case MIPS_INS_USW: + case MIPS_INS_ABSQ_S_PH: + case MIPS_INS_ABSQ_S_QB: + case MIPS_INS_ABSQ_S_W: + case MIPS_INS_ADD: + case MIPS_INS_ADDIUPC: + case MIPS_INS_ADDIUR1SP: + case MIPS_INS_ADDIUR2: + case MIPS_INS_ADDIUS5: + case MIPS_INS_ADDIUSP: + case MIPS_INS_ADDQH_PH: + case MIPS_INS_ADDQH_R_PH: + case MIPS_INS_ADDQH_R_W: + case MIPS_INS_ADDQH_W: + case MIPS_INS_ADDQ_PH: + case MIPS_INS_ADDQ_S_PH: + case MIPS_INS_ADDQ_S_W: + case MIPS_INS_ADDR_PS: + case MIPS_INS_ADDSC: + case MIPS_INS_ADDS_A_B: + case MIPS_INS_ADDS_A_D: + case MIPS_INS_ADDS_A_H: + case MIPS_INS_ADDS_A_W: + case MIPS_INS_ADDS_S_B: + case MIPS_INS_ADDS_S_D: + case MIPS_INS_ADDS_S_H: + case MIPS_INS_ADDS_S_W: + case MIPS_INS_ADDS_U_B: + case MIPS_INS_ADDS_U_D: + case MIPS_INS_ADDS_U_H: + case MIPS_INS_ADDS_U_W: + case MIPS_INS_ADDU16: + case MIPS_INS_ADDUH_QB: + case MIPS_INS_ADDUH_R_QB: + case MIPS_INS_ADDU: + case MIPS_INS_ADDU_PH: + case MIPS_INS_ADDU_QB: + case MIPS_INS_ADDU_S_PH: + case MIPS_INS_ADDU_S_QB: + case MIPS_INS_ADDVI_B: + case MIPS_INS_ADDVI_D: + case MIPS_INS_ADDVI_H: + case MIPS_INS_ADDVI_W: + case MIPS_INS_ADDV_B: + case MIPS_INS_ADDV_D: + case MIPS_INS_ADDV_H: + case MIPS_INS_ADDV_W: + case MIPS_INS_ADDWC: + case MIPS_INS_ADD_A_B: + case MIPS_INS_ADD_A_D: + case MIPS_INS_ADD_A_H: + case MIPS_INS_ADD_A_W: + case MIPS_INS_ADDI: + case MIPS_INS_ALUIPC: + case MIPS_INS_AND: + case MIPS_INS_AND16: + case MIPS_INS_ANDI16: + case MIPS_INS_ANDI_B: + case MIPS_INS_AND_V: + case MIPS_INS_APPEND: + case MIPS_INS_ASUB_S_B: + case MIPS_INS_ASUB_S_D: + case MIPS_INS_ASUB_S_H: + case MIPS_INS_ASUB_S_W: + case MIPS_INS_ASUB_U_B: + case MIPS_INS_ASUB_U_D: + case MIPS_INS_ASUB_U_H: + case MIPS_INS_ASUB_U_W: + case MIPS_INS_AUI: + case MIPS_INS_AUIPC: + case MIPS_INS_AVER_S_B: + case MIPS_INS_AVER_S_D: + case MIPS_INS_AVER_S_H: + case MIPS_INS_AVER_S_W: + case MIPS_INS_AVER_U_B: + case MIPS_INS_AVER_U_D: + case MIPS_INS_AVER_U_H: + case MIPS_INS_AVER_U_W: + case MIPS_INS_AVE_S_B: + case MIPS_INS_AVE_S_D: + case MIPS_INS_AVE_S_H: + case MIPS_INS_AVE_S_W: + case MIPS_INS_AVE_U_B: + case MIPS_INS_AVE_U_D: + case MIPS_INS_AVE_U_H: + case MIPS_INS_AVE_U_W: + case MIPS_INS_B16: + case MIPS_INS_BADDU: + case MIPS_INS_BAL: + case MIPS_INS_BALC: + case MIPS_INS_BALIGN: + case MIPS_INS_BALRSC: + case MIPS_INS_BBEQZC: + case MIPS_INS_BBIT0: + case MIPS_INS_BBIT032: + case MIPS_INS_BBIT1: + case MIPS_INS_BBIT132: + case MIPS_INS_BBNEZC: + case MIPS_INS_BC: + case MIPS_INS_BC16: + case MIPS_INS_BC1EQZ: + case MIPS_INS_BC1EQZC: + case MIPS_INS_BC1F: + case MIPS_INS_BC1FL: + case MIPS_INS_BC1NEZ: + case MIPS_INS_BC1NEZC: + case MIPS_INS_BC1T: + case MIPS_INS_BC1TL: + case MIPS_INS_BC2EQZ: + case MIPS_INS_BC2EQZC: + case MIPS_INS_BC2NEZ: + case MIPS_INS_BC2NEZC: + case MIPS_INS_BCLRI_B: + case MIPS_INS_BCLRI_D: + case MIPS_INS_BCLRI_H: + case MIPS_INS_BCLRI_W: + case MIPS_INS_BCLR_B: + case MIPS_INS_BCLR_D: + case MIPS_INS_BCLR_H: + case MIPS_INS_BCLR_W: + case MIPS_INS_BEQC: + case MIPS_INS_BEQIC: + case MIPS_INS_BEQZ16: + case MIPS_INS_BEQZALC: + case MIPS_INS_BEQZC: + case MIPS_INS_BEQZC16: + case MIPS_INS_BGEC: + case MIPS_INS_BGEIC: + case MIPS_INS_BGEIUC: + case MIPS_INS_BGEUC: + case MIPS_INS_BGEZ: + case MIPS_INS_BGEZAL: + case MIPS_INS_BGEZALC: + case MIPS_INS_BGEZALL: + case MIPS_INS_BGEZALS: + case MIPS_INS_BGEZC: + case MIPS_INS_BGEZL: + case MIPS_INS_BGTZ: + case MIPS_INS_BGTZALC: + case MIPS_INS_BGTZC: + case MIPS_INS_BGTZL: + case MIPS_INS_BINSLI_B: + case MIPS_INS_BINSLI_D: + case MIPS_INS_BINSLI_H: + case MIPS_INS_BINSLI_W: + case MIPS_INS_BINSL_B: + case MIPS_INS_BINSL_D: + case MIPS_INS_BINSL_H: + case MIPS_INS_BINSL_W: + case MIPS_INS_BINSRI_B: + case MIPS_INS_BINSRI_D: + case MIPS_INS_BINSRI_H: + case MIPS_INS_BINSRI_W: + case MIPS_INS_BINSR_B: + case MIPS_INS_BINSR_D: + case MIPS_INS_BINSR_H: + case MIPS_INS_BINSR_W: + case MIPS_INS_BITREV: + case MIPS_INS_BITREVW: + case MIPS_INS_BITSWAP: + case MIPS_INS_BLEZ: + case MIPS_INS_BLEZALC: + case MIPS_INS_BLEZC: + case MIPS_INS_BLEZL: + case MIPS_INS_BLTC: + case MIPS_INS_BLTIC: + case MIPS_INS_BLTIUC: + case MIPS_INS_BLTUC: + case MIPS_INS_BLTZ: + case MIPS_INS_BLTZAL: + case MIPS_INS_BLTZALC: + case MIPS_INS_BLTZALL: + case MIPS_INS_BLTZALS: + case MIPS_INS_BLTZC: + case MIPS_INS_BLTZL: + case MIPS_INS_BMNZI_B: + case MIPS_INS_BMNZ_V: + case MIPS_INS_BMZI_B: + case MIPS_INS_BMZ_V: + case MIPS_INS_BNEC: + case MIPS_INS_BNEGI_B: + case MIPS_INS_BNEGI_D: + case MIPS_INS_BNEGI_H: + case MIPS_INS_BNEGI_W: + case MIPS_INS_BNEG_B: + case MIPS_INS_BNEG_D: + case MIPS_INS_BNEG_H: + case MIPS_INS_BNEG_W: + case MIPS_INS_BNEIC: + case MIPS_INS_BNEZ16: + case MIPS_INS_BNEZALC: + case MIPS_INS_BNEZC: + case MIPS_INS_BNEZC16: + case MIPS_INS_BNVC: + case MIPS_INS_BNZ_B: + case MIPS_INS_BNZ_D: + case MIPS_INS_BNZ_H: + case MIPS_INS_BNZ_V: + case MIPS_INS_BNZ_W: + case MIPS_INS_BOVC: + case MIPS_INS_BPOSGE32: + case MIPS_INS_BPOSGE32C: + case MIPS_INS_BREAK: + case MIPS_INS_BREAK16: + case MIPS_INS_BRSC: + case MIPS_INS_BSELI_B: + case MIPS_INS_BSEL_V: + case MIPS_INS_BSETI_B: + case MIPS_INS_BSETI_D: + case MIPS_INS_BSETI_H: + case MIPS_INS_BSETI_W: + case MIPS_INS_BSET_B: + case MIPS_INS_BSET_D: + case MIPS_INS_BSET_H: + case MIPS_INS_BSET_W: + case MIPS_INS_BYTEREVW: + case MIPS_INS_BZ_B: + case MIPS_INS_BZ_D: + case MIPS_INS_BZ_H: + case MIPS_INS_BZ_V: + case MIPS_INS_BZ_W: + case MIPS_INS_BEQZ: + case MIPS_INS_BNEZ: + case MIPS_INS_BTEQZ: + case MIPS_INS_BTNEZ: + case MIPS_INS_CACHE: + case MIPS_INS_CACHEE: + case MIPS_INS_CEIL_L_D: + case MIPS_INS_CEIL_L_S: + case MIPS_INS_CEIL_W_D: + case MIPS_INS_CEIL_W_S: + case MIPS_INS_CEQI_B: + case MIPS_INS_CEQI_D: + case MIPS_INS_CEQI_H: + case MIPS_INS_CEQI_W: + case MIPS_INS_CEQ_B: + case MIPS_INS_CEQ_D: + case MIPS_INS_CEQ_H: + case MIPS_INS_CEQ_W: + case MIPS_INS_CFC1: + case MIPS_INS_CFC2: + case MIPS_INS_CFCMSA: + case MIPS_INS_CINS: + case MIPS_INS_CINS32: + case MIPS_INS_CLASS_D: + case MIPS_INS_CLASS_S: + case MIPS_INS_CLEI_S_B: + case MIPS_INS_CLEI_S_D: + case MIPS_INS_CLEI_S_H: + case MIPS_INS_CLEI_S_W: + case MIPS_INS_CLEI_U_B: + case MIPS_INS_CLEI_U_D: + case MIPS_INS_CLEI_U_H: + case MIPS_INS_CLEI_U_W: + case MIPS_INS_CLE_S_B: + case MIPS_INS_CLE_S_D: + case MIPS_INS_CLE_S_H: + case MIPS_INS_CLE_S_W: + case MIPS_INS_CLE_U_B: + case MIPS_INS_CLE_U_D: + case MIPS_INS_CLE_U_H: + case MIPS_INS_CLE_U_W: + case MIPS_INS_CLO: + case MIPS_INS_CLTI_S_B: + case MIPS_INS_CLTI_S_D: + case MIPS_INS_CLTI_S_H: + case MIPS_INS_CLTI_S_W: + case MIPS_INS_CLTI_U_B: + case MIPS_INS_CLTI_U_D: + case MIPS_INS_CLTI_U_H: + case MIPS_INS_CLTI_U_W: + case MIPS_INS_CLT_S_B: + case MIPS_INS_CLT_S_D: + case MIPS_INS_CLT_S_H: + case MIPS_INS_CLT_S_W: + case MIPS_INS_CLT_U_B: + case MIPS_INS_CLT_U_D: + case MIPS_INS_CLT_U_H: + case MIPS_INS_CLT_U_W: + case MIPS_INS_CLZ: + case MIPS_INS_CMPGDU_EQ_QB: + case MIPS_INS_CMPGDU_LE_QB: + case MIPS_INS_CMPGDU_LT_QB: + case MIPS_INS_CMPGU_EQ_QB: + case MIPS_INS_CMPGU_LE_QB: + case MIPS_INS_CMPGU_LT_QB: + case MIPS_INS_CMPU_EQ_QB: + case MIPS_INS_CMPU_LE_QB: + case MIPS_INS_CMPU_LT_QB: + case MIPS_INS_CMP_AF_D: + case MIPS_INS_CMP_AF_S: + case MIPS_INS_CMP_EQ_D: + case MIPS_INS_CMP_EQ_PH: + case MIPS_INS_CMP_EQ_S: + case MIPS_INS_CMP_LE_D: + case MIPS_INS_CMP_LE_PH: + case MIPS_INS_CMP_LE_S: + case MIPS_INS_CMP_LT_D: + case MIPS_INS_CMP_LT_PH: + case MIPS_INS_CMP_LT_S: + case MIPS_INS_CMP_SAF_D: + case MIPS_INS_CMP_SAF_S: + case MIPS_INS_CMP_SEQ_D: + case MIPS_INS_CMP_SEQ_S: + case MIPS_INS_CMP_SLE_D: + case MIPS_INS_CMP_SLE_S: + case MIPS_INS_CMP_SLT_D: + case MIPS_INS_CMP_SLT_S: + case MIPS_INS_CMP_SUEQ_D: + case MIPS_INS_CMP_SUEQ_S: + case MIPS_INS_CMP_SULE_D: + case MIPS_INS_CMP_SULE_S: + case MIPS_INS_CMP_SULT_D: + case MIPS_INS_CMP_SULT_S: + case MIPS_INS_CMP_SUN_D: + case MIPS_INS_CMP_SUN_S: + case MIPS_INS_CMP_UEQ_D: + case MIPS_INS_CMP_UEQ_S: + case MIPS_INS_CMP_ULE_D: + case MIPS_INS_CMP_ULE_S: + case MIPS_INS_CMP_ULT_D: + case MIPS_INS_CMP_ULT_S: + case MIPS_INS_CMP_UN_D: + case MIPS_INS_CMP_UN_S: + case MIPS_INS_COPY_S_B: + case MIPS_INS_COPY_S_D: + case MIPS_INS_COPY_S_H: + case MIPS_INS_COPY_S_W: + case MIPS_INS_COPY_U_B: + case MIPS_INS_COPY_U_H: + case MIPS_INS_COPY_U_W: + case MIPS_INS_CRC32B: + case MIPS_INS_CRC32CB: + case MIPS_INS_CRC32CD: + case MIPS_INS_CRC32CH: + case MIPS_INS_CRC32CW: + case MIPS_INS_CRC32D: + case MIPS_INS_CRC32H: + case MIPS_INS_CRC32W: + case MIPS_INS_CTC1: + case MIPS_INS_CTC2: + case MIPS_INS_CTCMSA: + case MIPS_INS_CVT_D_S: + case MIPS_INS_CVT_D_W: + case MIPS_INS_CVT_D_L: + case MIPS_INS_CVT_L_D: + case MIPS_INS_CVT_L_S: + case MIPS_INS_CVT_PS_PW: + case MIPS_INS_CVT_PS_S: + case MIPS_INS_CVT_PW_PS: + case MIPS_INS_CVT_S_D: + case MIPS_INS_CVT_S_L: + case MIPS_INS_CVT_S_PL: + case MIPS_INS_CVT_S_PU: + case MIPS_INS_CVT_S_W: + case MIPS_INS_CVT_W_D: + case MIPS_INS_CVT_W_S: + case MIPS_INS_C_EQ_D: + case MIPS_INS_C_EQ_S: + case MIPS_INS_C_F_D: + case MIPS_INS_C_F_S: + case MIPS_INS_C_LE_D: + case MIPS_INS_C_LE_S: + case MIPS_INS_C_LT_D: + case MIPS_INS_C_LT_S: + case MIPS_INS_C_NGE_D: + case MIPS_INS_C_NGE_S: + case MIPS_INS_C_NGLE_D: + case MIPS_INS_C_NGLE_S: + case MIPS_INS_C_NGL_D: + case MIPS_INS_C_NGL_S: + case MIPS_INS_C_NGT_D: + case MIPS_INS_C_NGT_S: + case MIPS_INS_C_OLE_D: + case MIPS_INS_C_OLE_S: + case MIPS_INS_C_OLT_D: + case MIPS_INS_C_OLT_S: + case MIPS_INS_C_SEQ_D: + case MIPS_INS_C_SEQ_S: + case MIPS_INS_C_SF_D: + case MIPS_INS_C_SF_S: + case MIPS_INS_C_UEQ_D: + case MIPS_INS_C_UEQ_S: + case MIPS_INS_C_ULE_D: + case MIPS_INS_C_ULE_S: + case MIPS_INS_C_ULT_D: + case MIPS_INS_C_ULT_S: + case MIPS_INS_C_UN_D: + case MIPS_INS_C_UN_S: + case MIPS_INS_CMP: + case MIPS_INS_CMPI: + case MIPS_INS_DADD: + case MIPS_INS_DADDI: + case MIPS_INS_DADDIU: + case MIPS_INS_DADDU: + case MIPS_INS_DAHI: + case MIPS_INS_DALIGN: + case MIPS_INS_DATI: + case MIPS_INS_DAUI: + case MIPS_INS_DBITSWAP: + case MIPS_INS_DCLO: + case MIPS_INS_DCLZ: + case MIPS_INS_DERET: + case MIPS_INS_DEXT: + case MIPS_INS_DEXTM: + case MIPS_INS_DEXTU: + case MIPS_INS_DI: + case MIPS_INS_DINS: + case MIPS_INS_DINSM: + case MIPS_INS_DINSU: + case MIPS_INS_DIV_S_B: + case MIPS_INS_DIV_S_D: + case MIPS_INS_DIV_S_H: + case MIPS_INS_DIV_S_W: + case MIPS_INS_DIV_U_B: + case MIPS_INS_DIV_U_D: + case MIPS_INS_DIV_U_H: + case MIPS_INS_DIV_U_W: + case MIPS_INS_DLSA: + case MIPS_INS_DMFC0: + case MIPS_INS_DMFC1: + case MIPS_INS_DMFC2: + case MIPS_INS_DMFGC0: + case MIPS_INS_DMOD: + case MIPS_INS_DMODU: + case MIPS_INS_DMT: + case MIPS_INS_DMTC0: + case MIPS_INS_DMTC1: + case MIPS_INS_DMTC2: + case MIPS_INS_DMTGC0: + case MIPS_INS_DMUH: + case MIPS_INS_DMUHU: + case MIPS_INS_DMULT: + case MIPS_INS_DMULTU: + case MIPS_INS_DMULU: + case MIPS_INS_DOTP_S_D: + case MIPS_INS_DOTP_S_H: + case MIPS_INS_DOTP_S_W: + case MIPS_INS_DOTP_U_D: + case MIPS_INS_DOTP_U_H: + case MIPS_INS_DOTP_U_W: + case MIPS_INS_DPADD_S_D: + case MIPS_INS_DPADD_S_H: + case MIPS_INS_DPADD_S_W: + case MIPS_INS_DPADD_U_D: + case MIPS_INS_DPADD_U_H: + case MIPS_INS_DPADD_U_W: + case MIPS_INS_DPAQX_SA_W_PH: + case MIPS_INS_DPAQX_S_W_PH: + case MIPS_INS_DPAQ_SA_L_W: + case MIPS_INS_DPAQ_S_W_PH: + case MIPS_INS_DPAU_H_QBL: + case MIPS_INS_DPAU_H_QBR: + case MIPS_INS_DPAX_W_PH: + case MIPS_INS_DPA_W_PH: + case MIPS_INS_DPOP: + case MIPS_INS_DPSQX_SA_W_PH: + case MIPS_INS_DPSQX_S_W_PH: + case MIPS_INS_DPSQ_SA_L_W: + case MIPS_INS_DPSQ_S_W_PH: + case MIPS_INS_DPSUB_S_D: + case MIPS_INS_DPSUB_S_H: + case MIPS_INS_DPSUB_S_W: + case MIPS_INS_DPSUB_U_D: + case MIPS_INS_DPSUB_U_H: + case MIPS_INS_DPSUB_U_W: + case MIPS_INS_DPSU_H_QBL: + case MIPS_INS_DPSU_H_QBR: + case MIPS_INS_DPSX_W_PH: + case MIPS_INS_DPS_W_PH: + case MIPS_INS_DROTR: + case MIPS_INS_DROTR32: + case MIPS_INS_DROTRV: + case MIPS_INS_DSBH: + case MIPS_INS_DSHD: + case MIPS_INS_DSLL: + case MIPS_INS_DSLL32: + case MIPS_INS_DSLLV: + case MIPS_INS_DSRA: + case MIPS_INS_DSRA32: + case MIPS_INS_DSRAV: + case MIPS_INS_DSRL: + case MIPS_INS_DSRL32: + case MIPS_INS_DSRLV: + case MIPS_INS_DSUB: + case MIPS_INS_DSUBU: + case MIPS_INS_DVP: + case MIPS_INS_DVPE: + case MIPS_INS_EHB: + case MIPS_INS_EI: + case MIPS_INS_EMT: + case MIPS_INS_ERET: + case MIPS_INS_ERETNC: + case MIPS_INS_EVP: + case MIPS_INS_EVPE: + case MIPS_INS_EXT: + case MIPS_INS_EXTP: + case MIPS_INS_EXTPDP: + case MIPS_INS_EXTPDPV: + case MIPS_INS_EXTPV: + case MIPS_INS_EXTRV_RS_W: + case MIPS_INS_EXTRV_R_W: + case MIPS_INS_EXTRV_S_H: + case MIPS_INS_EXTRV_W: + case MIPS_INS_EXTR_RS_W: + case MIPS_INS_EXTR_R_W: + case MIPS_INS_EXTR_S_H: + case MIPS_INS_EXTR_W: + case MIPS_INS_EXTS: + case MIPS_INS_EXTS32: + case MIPS_INS_EXTW: + case MIPS_INS_ABS_D: + case MIPS_INS_ABS_S: + case MIPS_INS_FADD_D: + case MIPS_INS_ADD_D: + case MIPS_INS_ADD_PS: + case MIPS_INS_ADD_S: + case MIPS_INS_FADD_W: + case MIPS_INS_FCAF_D: + case MIPS_INS_FCAF_W: + case MIPS_INS_FCEQ_D: + case MIPS_INS_FCEQ_W: + case MIPS_INS_FCLASS_D: + case MIPS_INS_FCLASS_W: + case MIPS_INS_FCLE_D: + case MIPS_INS_FCLE_W: + case MIPS_INS_FCLT_D: + case MIPS_INS_FCLT_W: + case MIPS_INS_FCNE_D: + case MIPS_INS_FCNE_W: + case MIPS_INS_FCOR_D: + case MIPS_INS_FCOR_W: + case MIPS_INS_FCUEQ_D: + case MIPS_INS_FCUEQ_W: + case MIPS_INS_FCULE_D: + case MIPS_INS_FCULE_W: + case MIPS_INS_FCULT_D: + case MIPS_INS_FCULT_W: + case MIPS_INS_FCUNE_D: + case MIPS_INS_FCUNE_W: + case MIPS_INS_FCUN_D: + case MIPS_INS_FCUN_W: + case MIPS_INS_FDIV_D: + case MIPS_INS_DIV_D: + case MIPS_INS_DIV_S: + case MIPS_INS_FDIV_W: + case MIPS_INS_FEXDO_H: + case MIPS_INS_FEXDO_W: + case MIPS_INS_FEXP2_D: + case MIPS_INS_FEXP2_W: + case MIPS_INS_FEXUPL_D: + case MIPS_INS_FEXUPL_W: + case MIPS_INS_FEXUPR_D: + case MIPS_INS_FEXUPR_W: + case MIPS_INS_FFINT_S_D: + case MIPS_INS_FFINT_S_W: + case MIPS_INS_FFINT_U_D: + case MIPS_INS_FFINT_U_W: + case MIPS_INS_FFQL_D: + case MIPS_INS_FFQL_W: + case MIPS_INS_FFQR_D: + case MIPS_INS_FFQR_W: + case MIPS_INS_FILL_B: + case MIPS_INS_FILL_D: + case MIPS_INS_FILL_H: + case MIPS_INS_FILL_W: + case MIPS_INS_FLOG2_D: + case MIPS_INS_FLOG2_W: + case MIPS_INS_FLOOR_L_D: + case MIPS_INS_FLOOR_L_S: + case MIPS_INS_FLOOR_W_D: + case MIPS_INS_FLOOR_W_S: + case MIPS_INS_FMADD_D: + case MIPS_INS_FMADD_W: + case MIPS_INS_FMAX_A_D: + case MIPS_INS_FMAX_A_W: + case MIPS_INS_FMAX_D: + case MIPS_INS_FMAX_W: + case MIPS_INS_FMIN_A_D: + case MIPS_INS_FMIN_A_W: + case MIPS_INS_FMIN_D: + case MIPS_INS_FMIN_W: + case MIPS_INS_MOV_D: + case MIPS_INS_MOV_S: + case MIPS_INS_FMSUB_D: + case MIPS_INS_FMSUB_W: + case MIPS_INS_FMUL_D: + case MIPS_INS_MUL_D: + case MIPS_INS_MUL_PS: + case MIPS_INS_MUL_S: + case MIPS_INS_FMUL_W: + case MIPS_INS_NEG_D: + case MIPS_INS_NEG_S: + case MIPS_INS_FORK: + case MIPS_INS_FRCP_D: + case MIPS_INS_FRCP_W: + case MIPS_INS_FRINT_D: + case MIPS_INS_FRINT_W: + case MIPS_INS_FRSQRT_D: + case MIPS_INS_FRSQRT_W: + case MIPS_INS_FSAF_D: + case MIPS_INS_FSAF_W: + case MIPS_INS_FSEQ_D: + case MIPS_INS_FSEQ_W: + case MIPS_INS_FSLE_D: + case MIPS_INS_FSLE_W: + case MIPS_INS_FSLT_D: + case MIPS_INS_FSLT_W: + case MIPS_INS_FSNE_D: + case MIPS_INS_FSNE_W: + case MIPS_INS_FSOR_D: + case MIPS_INS_FSOR_W: + case MIPS_INS_FSQRT_D: + case MIPS_INS_SQRT_D: + case MIPS_INS_SQRT_S: + case MIPS_INS_FSQRT_W: + case MIPS_INS_FSUB_D: + case MIPS_INS_SUB_D: + case MIPS_INS_SUB_PS: + case MIPS_INS_SUB_S: + case MIPS_INS_FSUB_W: + case MIPS_INS_FSUEQ_D: + case MIPS_INS_FSUEQ_W: + case MIPS_INS_FSULE_D: + case MIPS_INS_FSULE_W: + case MIPS_INS_FSULT_D: + case MIPS_INS_FSULT_W: + case MIPS_INS_FSUNE_D: + case MIPS_INS_FSUNE_W: + case MIPS_INS_FSUN_D: + case MIPS_INS_FSUN_W: + case MIPS_INS_FTINT_S_D: + case MIPS_INS_FTINT_S_W: + case MIPS_INS_FTINT_U_D: + case MIPS_INS_FTINT_U_W: + case MIPS_INS_FTQ_H: + case MIPS_INS_FTQ_W: + case MIPS_INS_FTRUNC_S_D: + case MIPS_INS_FTRUNC_S_W: + case MIPS_INS_FTRUNC_U_D: + case MIPS_INS_FTRUNC_U_W: + case MIPS_INS_GINVI: + case MIPS_INS_GINVT: + case MIPS_INS_HADD_S_D: + case MIPS_INS_HADD_S_H: + case MIPS_INS_HADD_S_W: + case MIPS_INS_HADD_U_D: + case MIPS_INS_HADD_U_H: + case MIPS_INS_HADD_U_W: + case MIPS_INS_HSUB_S_D: + case MIPS_INS_HSUB_S_H: + case MIPS_INS_HSUB_S_W: + case MIPS_INS_HSUB_U_D: + case MIPS_INS_HSUB_U_H: + case MIPS_INS_HSUB_U_W: + case MIPS_INS_HYPCALL: + case MIPS_INS_ILVEV_B: + case MIPS_INS_ILVEV_D: + case MIPS_INS_ILVEV_H: + case MIPS_INS_ILVEV_W: + case MIPS_INS_ILVL_B: + case MIPS_INS_ILVL_D: + case MIPS_INS_ILVL_H: + case MIPS_INS_ILVL_W: + case MIPS_INS_ILVOD_B: + case MIPS_INS_ILVOD_D: + case MIPS_INS_ILVOD_H: + case MIPS_INS_ILVOD_W: + case MIPS_INS_ILVR_B: + case MIPS_INS_ILVR_D: + case MIPS_INS_ILVR_H: + case MIPS_INS_ILVR_W: + case MIPS_INS_INS: + case MIPS_INS_INSERT_B: + case MIPS_INS_INSERT_D: + case MIPS_INS_INSERT_H: + case MIPS_INS_INSERT_W: + case MIPS_INS_INSV: + case MIPS_INS_INSVE_B: + case MIPS_INS_INSVE_D: + case MIPS_INS_INSVE_H: + case MIPS_INS_INSVE_W: + case MIPS_INS_J: + case MIPS_INS_JALR: + case MIPS_INS_JALRC: + case MIPS_INS_JALRC_HB: + case MIPS_INS_JALRS16: + case MIPS_INS_JALRS: + case MIPS_INS_JALR_HB: + case MIPS_INS_JALS: + case MIPS_INS_JALX: + case MIPS_INS_JIALC: + case MIPS_INS_JIC: + case MIPS_INS_JR: + case MIPS_INS_JR16: + case MIPS_INS_JRADDIUSP: + case MIPS_INS_JRC: + case MIPS_INS_JRC16: + case MIPS_INS_JRCADDIUSP: + case MIPS_INS_JR_HB: + case MIPS_INS_LAPC_H: + case MIPS_INS_LAPC_B: + case MIPS_INS_LB: + case MIPS_INS_LBE: + case MIPS_INS_LBU16: + case MIPS_INS_LBU: + case MIPS_INS_LBUX: + case MIPS_INS_LBX: + case MIPS_INS_LBUE: + case MIPS_INS_LDC1: + case MIPS_INS_LDC2: + case MIPS_INS_LDC3: + case MIPS_INS_LDI_B: + case MIPS_INS_LDI_D: + case MIPS_INS_LDI_H: + case MIPS_INS_LDI_W: + case MIPS_INS_LDL: + case MIPS_INS_LDPC: + case MIPS_INS_LDR: + case MIPS_INS_LDXC1: + case MIPS_INS_LD_B: + case MIPS_INS_LD_D: + case MIPS_INS_LD_H: + case MIPS_INS_LD_W: + case MIPS_INS_LH: + case MIPS_INS_LHE: + case MIPS_INS_LHU16: + case MIPS_INS_LHU: + case MIPS_INS_LHUXS: + case MIPS_INS_LHUX: + case MIPS_INS_LHX: + case MIPS_INS_LHXS: + case MIPS_INS_LHUE: + case MIPS_INS_LI16: + case MIPS_INS_LL: + case MIPS_INS_LLD: + case MIPS_INS_LLE: + case MIPS_INS_LLWP: + case MIPS_INS_LSA: + case MIPS_INS_LUI: + case MIPS_INS_LUXC1: + case MIPS_INS_LW: + case MIPS_INS_LW16: + case MIPS_INS_LWC1: + case MIPS_INS_LWC2: + case MIPS_INS_LWC3: + case MIPS_INS_LWE: + case MIPS_INS_LWL: + case MIPS_INS_LWLE: + case MIPS_INS_LWM16: + case MIPS_INS_LWM32: + case MIPS_INS_LWPC: + case MIPS_INS_LWP: + case MIPS_INS_LWR: + case MIPS_INS_LWRE: + case MIPS_INS_LWUPC: + case MIPS_INS_LWU: + case MIPS_INS_LWX: + case MIPS_INS_LWXC1: + case MIPS_INS_LWXS: + case MIPS_INS_MADD: + case MIPS_INS_MADDF_D: + case MIPS_INS_MADDF_S: + case MIPS_INS_MADDR_Q_H: + case MIPS_INS_MADDR_Q_W: + case MIPS_INS_MADDU: + case MIPS_INS_MADDV_B: + case MIPS_INS_MADDV_D: + case MIPS_INS_MADDV_H: + case MIPS_INS_MADDV_W: + case MIPS_INS_MADD_D: + case MIPS_INS_MADD_Q_H: + case MIPS_INS_MADD_Q_W: + case MIPS_INS_MADD_S: + case MIPS_INS_MAQ_SA_W_PHL: + case MIPS_INS_MAQ_SA_W_PHR: + case MIPS_INS_MAQ_S_W_PHL: + case MIPS_INS_MAQ_S_W_PHR: + case MIPS_INS_MAXA_D: + case MIPS_INS_MAXA_S: + case MIPS_INS_MAXI_S_B: + case MIPS_INS_MAXI_S_D: + case MIPS_INS_MAXI_S_H: + case MIPS_INS_MAXI_S_W: + case MIPS_INS_MAXI_U_B: + case MIPS_INS_MAXI_U_D: + case MIPS_INS_MAXI_U_H: + case MIPS_INS_MAXI_U_W: + case MIPS_INS_MAX_A_B: + case MIPS_INS_MAX_A_D: + case MIPS_INS_MAX_A_H: + case MIPS_INS_MAX_A_W: + case MIPS_INS_MAX_D: + case MIPS_INS_MAX_S: + case MIPS_INS_MAX_S_B: + case MIPS_INS_MAX_S_D: + case MIPS_INS_MAX_S_H: + case MIPS_INS_MAX_S_W: + case MIPS_INS_MAX_U_B: + case MIPS_INS_MAX_U_D: + case MIPS_INS_MAX_U_H: + case MIPS_INS_MAX_U_W: + case MIPS_INS_MFC0: + case MIPS_INS_MFC1: + case MIPS_INS_MFC2: + case MIPS_INS_MFGC0: + case MIPS_INS_MFHC0: + case MIPS_INS_MFHC1: + case MIPS_INS_MFHC2: + case MIPS_INS_MFHGC0: + case MIPS_INS_MFHI: + case MIPS_INS_MFHI16: + case MIPS_INS_MFLO: + case MIPS_INS_MFLO16: + case MIPS_INS_MFTR: + case MIPS_INS_MINA_D: + case MIPS_INS_MINA_S: + case MIPS_INS_MINI_S_B: + case MIPS_INS_MINI_S_D: + case MIPS_INS_MINI_S_H: + case MIPS_INS_MINI_S_W: + case MIPS_INS_MINI_U_B: + case MIPS_INS_MINI_U_D: + case MIPS_INS_MINI_U_H: + case MIPS_INS_MINI_U_W: + case MIPS_INS_MIN_A_B: + case MIPS_INS_MIN_A_D: + case MIPS_INS_MIN_A_H: + case MIPS_INS_MIN_A_W: + case MIPS_INS_MIN_D: + case MIPS_INS_MIN_S: + case MIPS_INS_MIN_S_B: + case MIPS_INS_MIN_S_D: + case MIPS_INS_MIN_S_H: + case MIPS_INS_MIN_S_W: + case MIPS_INS_MIN_U_B: + case MIPS_INS_MIN_U_D: + case MIPS_INS_MIN_U_H: + case MIPS_INS_MIN_U_W: + case MIPS_INS_MOD: + case MIPS_INS_MODSUB: + case MIPS_INS_MODU: + case MIPS_INS_MOD_S_B: + case MIPS_INS_MOD_S_D: + case MIPS_INS_MOD_S_H: + case MIPS_INS_MOD_S_W: + case MIPS_INS_MOD_U_B: + case MIPS_INS_MOD_U_D: + case MIPS_INS_MOD_U_H: + case MIPS_INS_MOD_U_W: + case MIPS_INS_MOVE: + case MIPS_INS_MOVE16: + case MIPS_INS_MOVE_BALC: + case MIPS_INS_MOVEP: + case MIPS_INS_MOVE_V: + case MIPS_INS_MOVF_D: + case MIPS_INS_MOVF: + case MIPS_INS_MOVF_S: + case MIPS_INS_MOVN_D: + case MIPS_INS_MOVN: + case MIPS_INS_MOVN_S: + case MIPS_INS_MOVT_D: + case MIPS_INS_MOVT: + case MIPS_INS_MOVT_S: + case MIPS_INS_MOVZ_D: + case MIPS_INS_MOVZ: + case MIPS_INS_MOVZ_S: + case MIPS_INS_MSUB: + case MIPS_INS_MSUBF_D: + case MIPS_INS_MSUBF_S: + case MIPS_INS_MSUBR_Q_H: + case MIPS_INS_MSUBR_Q_W: + case MIPS_INS_MSUBU: + case MIPS_INS_MSUBV_B: + case MIPS_INS_MSUBV_D: + case MIPS_INS_MSUBV_H: + case MIPS_INS_MSUBV_W: + case MIPS_INS_MSUB_D: + case MIPS_INS_MSUB_Q_H: + case MIPS_INS_MSUB_Q_W: + case MIPS_INS_MSUB_S: + case MIPS_INS_MTC0: + case MIPS_INS_MTC1: + case MIPS_INS_MTC2: + case MIPS_INS_MTGC0: + case MIPS_INS_MTHC0: + case MIPS_INS_MTHC1: + case MIPS_INS_MTHC2: + case MIPS_INS_MTHGC0: + case MIPS_INS_MTHI: + case MIPS_INS_MTHLIP: + case MIPS_INS_MTLO: + case MIPS_INS_MTM0: + case MIPS_INS_MTM1: + case MIPS_INS_MTM2: + case MIPS_INS_MTP0: + case MIPS_INS_MTP1: + case MIPS_INS_MTP2: + case MIPS_INS_MTTR: + case MIPS_INS_MUH: + case MIPS_INS_MUHU: + case MIPS_INS_MULEQ_S_W_PHL: + case MIPS_INS_MULEQ_S_W_PHR: + case MIPS_INS_MULEU_S_PH_QBL: + case MIPS_INS_MULEU_S_PH_QBR: + case MIPS_INS_MULQ_RS_PH: + case MIPS_INS_MULQ_RS_W: + case MIPS_INS_MULQ_S_PH: + case MIPS_INS_MULQ_S_W: + case MIPS_INS_MULR_PS: + case MIPS_INS_MULR_Q_H: + case MIPS_INS_MULR_Q_W: + case MIPS_INS_MULSAQ_S_W_PH: + case MIPS_INS_MULSA_W_PH: + case MIPS_INS_MULT: + case MIPS_INS_MULTU: + case MIPS_INS_MULU: + case MIPS_INS_MULV_B: + case MIPS_INS_MULV_D: + case MIPS_INS_MULV_H: + case MIPS_INS_MULV_W: + case MIPS_INS_MUL_PH: + case MIPS_INS_MUL_Q_H: + case MIPS_INS_MUL_Q_W: + case MIPS_INS_MUL_S_PH: + case MIPS_INS_NLOC_B: + case MIPS_INS_NLOC_D: + case MIPS_INS_NLOC_H: + case MIPS_INS_NLOC_W: + case MIPS_INS_NLZC_B: + case MIPS_INS_NLZC_D: + case MIPS_INS_NLZC_H: + case MIPS_INS_NLZC_W: + case MIPS_INS_NMADD_D: + case MIPS_INS_NMADD_S: + case MIPS_INS_NMSUB_D: + case MIPS_INS_NMSUB_S: + case MIPS_INS_NOP32: + case MIPS_INS_NOP: + case MIPS_INS_NORI_B: + case MIPS_INS_NOR_V: + case MIPS_INS_NOT16: + case MIPS_INS_NOT: + case MIPS_INS_NEG: + case MIPS_INS_OR: + case MIPS_INS_OR16: + case MIPS_INS_ORI_B: + case MIPS_INS_ORI: + case MIPS_INS_OR_V: + case MIPS_INS_PACKRL_PH: + case MIPS_INS_PAUSE: + case MIPS_INS_PCKEV_B: + case MIPS_INS_PCKEV_D: + case MIPS_INS_PCKEV_H: + case MIPS_INS_PCKEV_W: + case MIPS_INS_PCKOD_B: + case MIPS_INS_PCKOD_D: + case MIPS_INS_PCKOD_H: + case MIPS_INS_PCKOD_W: + case MIPS_INS_PCNT_B: + case MIPS_INS_PCNT_D: + case MIPS_INS_PCNT_H: + case MIPS_INS_PCNT_W: + case MIPS_INS_PICK_PH: + case MIPS_INS_PICK_QB: + case MIPS_INS_PLL_PS: + case MIPS_INS_PLU_PS: + case MIPS_INS_POP: + case MIPS_INS_PRECEQU_PH_QBL: + case MIPS_INS_PRECEQU_PH_QBLA: + case MIPS_INS_PRECEQU_PH_QBR: + case MIPS_INS_PRECEQU_PH_QBRA: + case MIPS_INS_PRECEQ_W_PHL: + case MIPS_INS_PRECEQ_W_PHR: + case MIPS_INS_PRECEU_PH_QBL: + case MIPS_INS_PRECEU_PH_QBLA: + case MIPS_INS_PRECEU_PH_QBR: + case MIPS_INS_PRECEU_PH_QBRA: + case MIPS_INS_PRECRQU_S_QB_PH: + case MIPS_INS_PRECRQ_PH_W: + case MIPS_INS_PRECRQ_QB_PH: + case MIPS_INS_PRECRQ_RS_PH_W: + case MIPS_INS_PRECR_QB_PH: + case MIPS_INS_PRECR_SRA_PH_W: + case MIPS_INS_PRECR_SRA_R_PH_W: + case MIPS_INS_PREF: + case MIPS_INS_PREFE: + case MIPS_INS_PREFX: + case MIPS_INS_PREPEND: + case MIPS_INS_PUL_PS: + case MIPS_INS_PUU_PS: + case MIPS_INS_RADDU_W_QB: + case MIPS_INS_RDDSP: + case MIPS_INS_RDHWR: + case MIPS_INS_RDPGPR: + case MIPS_INS_RECIP_D: + case MIPS_INS_RECIP_S: + case MIPS_INS_REPLV_PH: + case MIPS_INS_REPLV_QB: + case MIPS_INS_REPL_PH: + case MIPS_INS_REPL_QB: + case MIPS_INS_RESTORE_JRC: + case MIPS_INS_RESTORE: + case MIPS_INS_RINT_D: + case MIPS_INS_RINT_S: + case MIPS_INS_ROTR: + case MIPS_INS_ROTRV: + case MIPS_INS_ROTX: + case MIPS_INS_ROUND_L_D: + case MIPS_INS_ROUND_L_S: + case MIPS_INS_ROUND_W_D: + case MIPS_INS_ROUND_W_S: + case MIPS_INS_RSQRT_D: + case MIPS_INS_RSQRT_S: + case MIPS_INS_SAT_S_B: + case MIPS_INS_SAT_S_D: + case MIPS_INS_SAT_S_H: + case MIPS_INS_SAT_S_W: + case MIPS_INS_SAT_U_B: + case MIPS_INS_SAT_U_D: + case MIPS_INS_SAT_U_H: + case MIPS_INS_SAT_U_W: + case MIPS_INS_SAVE: + case MIPS_INS_SB: + case MIPS_INS_SB16: + case MIPS_INS_SBE: + case MIPS_INS_SBX: + case MIPS_INS_SC: + case MIPS_INS_SCD: + case MIPS_INS_SCE: + case MIPS_INS_SCWP: + case MIPS_INS_SDBBP: + case MIPS_INS_SDBBP16: + case MIPS_INS_SDC1: + case MIPS_INS_SDC2: + case MIPS_INS_SDC3: + case MIPS_INS_SDL: + case MIPS_INS_SDR: + case MIPS_INS_SDXC1: + case MIPS_INS_SEB: + case MIPS_INS_SEH: + case MIPS_INS_SELEQZ: + case MIPS_INS_SELEQZ_D: + case MIPS_INS_SELEQZ_S: + case MIPS_INS_SELNEZ: + case MIPS_INS_SELNEZ_D: + case MIPS_INS_SELNEZ_S: + case MIPS_INS_SEL_D: + case MIPS_INS_SEL_S: + case MIPS_INS_SEQI: + case MIPS_INS_SH: + case MIPS_INS_SH16: + case MIPS_INS_SHE: + case MIPS_INS_SHF_B: + case MIPS_INS_SHF_H: + case MIPS_INS_SHF_W: + case MIPS_INS_SHILO: + case MIPS_INS_SHILOV: + case MIPS_INS_SHLLV_PH: + case MIPS_INS_SHLLV_QB: + case MIPS_INS_SHLLV_S_PH: + case MIPS_INS_SHLLV_S_W: + case MIPS_INS_SHLL_PH: + case MIPS_INS_SHLL_QB: + case MIPS_INS_SHLL_S_PH: + case MIPS_INS_SHLL_S_W: + case MIPS_INS_SHRAV_PH: + case MIPS_INS_SHRAV_QB: + case MIPS_INS_SHRAV_R_PH: + case MIPS_INS_SHRAV_R_QB: + case MIPS_INS_SHRAV_R_W: + case MIPS_INS_SHRA_PH: + case MIPS_INS_SHRA_QB: + case MIPS_INS_SHRA_R_PH: + case MIPS_INS_SHRA_R_QB: + case MIPS_INS_SHRA_R_W: + case MIPS_INS_SHRLV_PH: + case MIPS_INS_SHRLV_QB: + case MIPS_INS_SHRL_PH: + case MIPS_INS_SHRL_QB: + case MIPS_INS_SHXS: + case MIPS_INS_SHX: + case MIPS_INS_SIGRIE: + case MIPS_INS_SLDI_B: + case MIPS_INS_SLDI_D: + case MIPS_INS_SLDI_H: + case MIPS_INS_SLDI_W: + case MIPS_INS_SLD_B: + case MIPS_INS_SLD_D: + case MIPS_INS_SLD_H: + case MIPS_INS_SLD_W: + case MIPS_INS_SLL: + case MIPS_INS_SLL16: + case MIPS_INS_SLLI_B: + case MIPS_INS_SLLI_D: + case MIPS_INS_SLLI_H: + case MIPS_INS_SLLI_W: + case MIPS_INS_SLLV: + case MIPS_INS_SLL_B: + case MIPS_INS_SLL_D: + case MIPS_INS_SLL_H: + case MIPS_INS_SLL_W: + case MIPS_INS_SLTIU: + case MIPS_INS_SLTI: + case MIPS_INS_SNEI: + case MIPS_INS_SOV: + case MIPS_INS_SPLATI_B: + case MIPS_INS_SPLATI_D: + case MIPS_INS_SPLATI_H: + case MIPS_INS_SPLATI_W: + case MIPS_INS_SPLAT_B: + case MIPS_INS_SPLAT_D: + case MIPS_INS_SPLAT_H: + case MIPS_INS_SPLAT_W: + case MIPS_INS_SRA: + case MIPS_INS_SRAI_B: + case MIPS_INS_SRAI_D: + case MIPS_INS_SRAI_H: + case MIPS_INS_SRAI_W: + case MIPS_INS_SRARI_B: + case MIPS_INS_SRARI_D: + case MIPS_INS_SRARI_H: + case MIPS_INS_SRARI_W: + case MIPS_INS_SRAR_B: + case MIPS_INS_SRAR_D: + case MIPS_INS_SRAR_H: + case MIPS_INS_SRAR_W: + case MIPS_INS_SRAV: + case MIPS_INS_SRA_B: + case MIPS_INS_SRA_D: + case MIPS_INS_SRA_H: + case MIPS_INS_SRA_W: + case MIPS_INS_SRL: + case MIPS_INS_SRL16: + case MIPS_INS_SRLI_B: + case MIPS_INS_SRLI_D: + case MIPS_INS_SRLI_H: + case MIPS_INS_SRLI_W: + case MIPS_INS_SRLRI_B: + case MIPS_INS_SRLRI_D: + case MIPS_INS_SRLRI_H: + case MIPS_INS_SRLRI_W: + case MIPS_INS_SRLR_B: + case MIPS_INS_SRLR_D: + case MIPS_INS_SRLR_H: + case MIPS_INS_SRLR_W: + case MIPS_INS_SRLV: + case MIPS_INS_SRL_B: + case MIPS_INS_SRL_D: + case MIPS_INS_SRL_H: + case MIPS_INS_SRL_W: + case MIPS_INS_SSNOP: + case MIPS_INS_ST_B: + case MIPS_INS_ST_D: + case MIPS_INS_ST_H: + case MIPS_INS_ST_W: + case MIPS_INS_SUB: + case MIPS_INS_SUBQH_PH: + case MIPS_INS_SUBQH_R_PH: + case MIPS_INS_SUBQH_R_W: + case MIPS_INS_SUBQH_W: + case MIPS_INS_SUBQ_PH: + case MIPS_INS_SUBQ_S_PH: + case MIPS_INS_SUBQ_S_W: + case MIPS_INS_SUBSUS_U_B: + case MIPS_INS_SUBSUS_U_D: + case MIPS_INS_SUBSUS_U_H: + case MIPS_INS_SUBSUS_U_W: + case MIPS_INS_SUBSUU_S_B: + case MIPS_INS_SUBSUU_S_D: + case MIPS_INS_SUBSUU_S_H: + case MIPS_INS_SUBSUU_S_W: + case MIPS_INS_SUBS_S_B: + case MIPS_INS_SUBS_S_D: + case MIPS_INS_SUBS_S_H: + case MIPS_INS_SUBS_S_W: + case MIPS_INS_SUBS_U_B: + case MIPS_INS_SUBS_U_D: + case MIPS_INS_SUBS_U_H: + case MIPS_INS_SUBS_U_W: + case MIPS_INS_SUBU16: + case MIPS_INS_SUBUH_QB: + case MIPS_INS_SUBUH_R_QB: + case MIPS_INS_SUBU_PH: + case MIPS_INS_SUBU_QB: + case MIPS_INS_SUBU_S_PH: + case MIPS_INS_SUBU_S_QB: + case MIPS_INS_SUBVI_B: + case MIPS_INS_SUBVI_D: + case MIPS_INS_SUBVI_H: + case MIPS_INS_SUBVI_W: + case MIPS_INS_SUBV_B: + case MIPS_INS_SUBV_D: + case MIPS_INS_SUBV_H: + case MIPS_INS_SUBV_W: + case MIPS_INS_SUXC1: + case MIPS_INS_SW: + case MIPS_INS_SW16: + case MIPS_INS_SWC1: + case MIPS_INS_SWC2: + case MIPS_INS_SWC3: + case MIPS_INS_SWE: + case MIPS_INS_SWL: + case MIPS_INS_SWLE: + case MIPS_INS_SWM16: + case MIPS_INS_SWM32: + case MIPS_INS_SWPC: + case MIPS_INS_SWP: + case MIPS_INS_SWR: + case MIPS_INS_SWRE: + case MIPS_INS_SWSP: + case MIPS_INS_SWXC1: + case MIPS_INS_SWXS: + case MIPS_INS_SWX: + case MIPS_INS_SYNC: + case MIPS_INS_SYNCI: + case MIPS_INS_SYSCALL: + case MIPS_INS_TEQ: + case MIPS_INS_TEQI: + case MIPS_INS_TGE: + case MIPS_INS_TGEI: + case MIPS_INS_TGEIU: + case MIPS_INS_TGEU: + case MIPS_INS_TLBGINV: + case MIPS_INS_TLBGINVF: + case MIPS_INS_TLBGP: + case MIPS_INS_TLBGR: + case MIPS_INS_TLBGWI: + case MIPS_INS_TLBGWR: + case MIPS_INS_TLBINV: + case MIPS_INS_TLBINVF: + case MIPS_INS_TLBP: + case MIPS_INS_TLBR: + case MIPS_INS_TLBWI: + case MIPS_INS_TLBWR: + case MIPS_INS_TLT: + case MIPS_INS_TLTI: + case MIPS_INS_TLTIU: + case MIPS_INS_TLTU: + case MIPS_INS_TNE: + case MIPS_INS_TNEI: + case MIPS_INS_TRUNC_L_D: + case MIPS_INS_TRUNC_L_S: + case MIPS_INS_UALH: + case MIPS_INS_UALWM: + case MIPS_INS_UALW: + case MIPS_INS_UASH: + case MIPS_INS_UASWM: + case MIPS_INS_UASW: + case MIPS_INS_V3MULU: + case MIPS_INS_VMM0: + case MIPS_INS_VMULU: + case MIPS_INS_VSHF_B: + case MIPS_INS_VSHF_D: + case MIPS_INS_VSHF_H: + case MIPS_INS_VSHF_W: + case MIPS_INS_WAIT: + case MIPS_INS_WRDSP: + case MIPS_INS_WRPGPR: + case MIPS_INS_WSBH: + case MIPS_INS_XOR: + case MIPS_INS_XOR16: + case MIPS_INS_XORI_B: + case MIPS_INS_XORI: + case MIPS_INS_XOR_V: + case MIPS_INS_YIELD: + default: + return NULL; + } +} + +RZ_IPI RzAnalysisILConfig *mips_il_config() { + return NULL; +} diff --git a/librz/arch/isa/mips/mips_internal.h b/librz/arch/isa/mips/mips_internal.h index dd2d3e5e40e..a00bb6e5895 100644 --- a/librz/arch/isa/mips/mips_internal.h +++ b/librz/arch/isa/mips/mips_internal.h @@ -1,13 +1,24 @@ -// SPDX-FileCopyrightText: 2012-2018 pancake +// SPDX-FileCopyrightText: 2024-2025 deroad // SPDX-License-Identifier: LGPL-3.0-only #ifndef MIPS_INTERNAL_H #define MIPS_INTERNAL_H -#include +#include #include #include +#define OPERAND(x) insn->detail->mips.operands[x] +#define REGID(x) insn->detail->mips.operands[x].reg +#define REG(x) cs_reg_name(*handle, insn->detail->mips.operands[x].reg) +#define IMM(x) insn->detail->mips.operands[x].imm +#define MEMBASE(x) cs_reg_name(*handle, insn->detail->mips.operands[x].mem.base) +#define MEMINDEX(x) insn->detail->mips.operands[x].mem.index +#define MEMDISP(x) insn->detail->mips.operands[x].mem.disp +#define OPCOUNT() insn->detail->mips.op_count + +RZ_IPI RzILOpEffect *mips_il(RZ_NONNULL cs_insn *insn); +RZ_IPI RzAnalysisILConfig *mips_il_config(); RZ_IPI int mips_assemble_opcode(const char *str, ut64 pc, ut8 *out); RZ_IPI int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn); diff --git a/librz/arch/meson.build b/librz/arch/meson.build index 8d52a1e1d7f..7e12365538a 100644 --- a/librz/arch/meson.build +++ b/librz/arch/meson.build @@ -219,6 +219,7 @@ arch_isa_sources = [ 'isa/mcore/mcore.c', 'isa/mips/mips_assembler.c', 'isa/mips/mips_esil.c', + 'isa/mips/mips_il.c', 'isa/msp430/msp430_disas.c', 'isa/msp430/msp430_il.c', 'isa/or1k/or1k_disas.c', diff --git a/librz/arch/p/analysis/analysis_mips_cs.c b/librz/arch/p/analysis/analysis_mips_cs.c index 734f5c02e23..3711edf9c96 100644 --- a/librz/arch/p/analysis/analysis_mips_cs.c +++ b/librz/arch/p/analysis/analysis_mips_cs.c @@ -1,4 +1,4 @@ -// SPDX-FileCopyrightText: 2024 deroad +// SPDX-FileCopyrightText: 2024-2025 deroad // SPDX-FileCopyrightText: 2013-2019 pancake // SPDX-License-Identifier: LGPL-3.0-only @@ -8,16 +8,6 @@ // http://www.mrc.uidaho.edu/mrc/people/jff/digital/MIPSir.html -#define OPERAND(x) insn->detail->mips.operands[x] -#define REGID(x) insn->detail->mips.operands[x].reg -#define REG(x) cs_reg_name(*handle, insn->detail->mips.operands[x].reg) -#define IMM(x) insn->detail->mips.operands[x].imm -#define MEMBASE(x) cs_reg_name(*handle, insn->detail->mips.operands[x].mem.base) -#define MEMINDEX(x) insn->detail->mips.operands[x].mem.index -#define MEMDISP(x) insn->detail->mips.operands[x].mem.disp -#define OPCOUNT() insn->detail->mips.op_count -// TODO scale and disp - #define SET_VAL(op, i) \ if ((i) < OPCOUNT() && OPERAND(i).type == MIPS_OP_IMM) { \ (op)->val = OPERAND(i).imm; \ @@ -247,6 +237,10 @@ static int mips_analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, co insn->op_str[0] ? " " : "", insn->op_str); } + if (mask & RZ_ANALYSIS_OP_MASK_IL) { + op->il_op = mips_il(insn); + } + op->id = insn->id; opsize = op->size = insn->size; op->refptr = 0; @@ -1021,7 +1015,7 @@ static bool mips_fini(void *user) { RzAnalysisPlugin rz_analysis_plugin_mips_cs = { .name = "mips", .desc = "Capstone MIPS analyzer", - .license = "BSD", + .license = "LGPL3", .esil = true, .arch = "mips", .get_reg_profile = mips_get_reg_profile, @@ -1031,6 +1025,7 @@ RzAnalysisPlugin rz_analysis_plugin_mips_cs = { .op = &mips_analyze_op, .init = mips_init, .fini = mips_fini, + .il_config = mips_il_config, }; #ifndef RZ_PLUGIN_INCORE