First draft

Author: romancardenas

.github/workflows/riscv-rt.yaml

@@ -1,6 +1,6 @@
 on:
   push:
-    branches: [ master, riscv-rt-asm ]
+    branches: [ master, vectored-rt ]
   pull_request:
   merge_group:
 
@@ -39,6 +39,8 @@ jobs:
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=s-mode
       - name : Build (single-hart)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=single-hart
+      - name : Build (v-trap)
+        run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --features=v-trap
       - name: Build (all features)
         run: RUSTFLAGS="-C link-arg=-Triscv-rt/examples/device.x" cargo build --package riscv-rt --target ${{ matrix.target }} --example ${{ matrix.example }} --all-features
 

riscv-rt/CHANGELOG.md

@@ -10,6 +10,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Added
 
 - Add `pre_init_trap` to detect early errors during the boot process.
+- Add `v-trap` feature to enable interrupt handling in vectored mode.
+- Add `interrupt` proc macro to help defining interrupt handlers.
+If `v-trap` feature is enabled, this macro also generates its corresponding trap.
 
 ### Changed
 

riscv-rt/Cargo.toml

@@ -12,13 +12,14 @@ license = "ISC"
 edition = "2021"
 links = "riscv-rt" # Prevent multiple versions of riscv-rt being linked
 
-[features]
-s-mode = []
-single-hart = []
-
 [dependencies]
 riscv = {path = "../riscv", version = "0.11.1"}
 riscv-rt-macros = { path = "macros", version = "0.2.1" }
 
 [dev-dependencies]
 panic-halt = "0.2.0"
+
+[features]
+s-mode = ["riscv-rt-macros/s-mode"]
+single-hart = []
+v-trap = ["riscv-rt-macros/v-trap"]

riscv-rt/examples/empty.rs

@@ -4,10 +4,16 @@
 extern crate panic_halt;
 extern crate riscv_rt;
 
-use riscv_rt::entry;
+use riscv_rt::{entry, interrupt};
 
 #[entry]
 fn main() -> ! {
     // do something here
     loop {}
 }
+
+#[interrupt]
+fn MachineSoft() {
+    // do something here
+    loop {}
+}

riscv-rt/link.x.in

@@ -28,6 +28,23 @@ PROVIDE(_max_hart_id = 0);
 PROVIDE(_hart_stack_size = 2K);
 PROVIDE(_heap_size = 0);
 
+/** TRAP ENTRY POINTS **/
+
+/* Default trap entry point. The riscv-rt crate provides a weak alias of this function,
+   which saves caller saved registers, calls _start_trap_rust, restores caller saved registers
+   and then returns. Users can override this alias by defining the symbol themselves */
+EXTERN(_start_trap);
+
+/* When vectored trap mode is enabled, each interrupt source must implement its own
+   trap entry point. By default, all interrupts start in _start_trap. However, users can
+   override these alias by defining the symbol themselves */
+PROVIDE(_start_SupervisorSoft_trap = _start_trap);
+PROVIDE(_start_MachineSoft_trap = _start_trap);
+PROVIDE(_start_SupervisorTimer_trap = _start_trap);
+PROVIDE(_start_MachineTimer_trap = _start_trap);
+PROVIDE(_start_SupervisorExternal_trap = _start_trap);
+PROVIDE(_start_MachineExternal_trap = _start_trap);
+
 /** EXCEPTION HANDLERS **/
 
 /* Default exception handler. The riscv-rt crate provides a weak alias of this function,

riscv-rt/macros/Cargo.toml

@@ -22,3 +22,7 @@ proc-macro2 = "1.0"
 [dependencies.syn]
 version = "1.0"
 features = ["extra-traits", "full"]
+
+[features]
+s-mode = []
+v-trap = []

riscv-rt/macros/src/lib.rs

@@ -312,3 +312,136 @@ pub fn loop_global_asm(input: TokenStream) -> TokenStream {
     let res = format!("core::arch::global_asm!(\n\"{}\"\n);", instructions);
     res.parse().unwrap()
 }
+
+enum RiscvArch {
+    Rv32,
+    Rv64,
+}
+
+#[proc_macro_attribute]
+pub fn interrupt_riscv32(args: TokenStream, input: TokenStream) -> TokenStream {
+    interrupt(args, input, RiscvArch::Rv32)
+}
+
+#[proc_macro_attribute]
+pub fn interrupt_riscv64(args: TokenStream, input: TokenStream) -> TokenStream {
+    interrupt(args, input, RiscvArch::Rv64)
+}
+
+fn interrupt(args: TokenStream, input: TokenStream, _arch: RiscvArch) -> TokenStream {
+    let f = parse_macro_input!(input as ItemFn);
+
+    // check the function signature
+    let valid_signature = f.sig.constness.is_none()
+        && f.sig.asyncness.is_none()
+        && f.vis == Visibility::Inherited
+        && f.sig.abi.is_none()
+        && f.sig.generics.params.is_empty()
+        && f.sig.generics.where_clause.is_none()
+        && f.sig.variadic.is_none()
+        && match f.sig.output {
+            ReturnType::Default => true,
+            ReturnType::Type(_, ref ty) => matches!(**ty, Type::Never(_)),
+        };
+
+    if !valid_signature {
+        return parse::Error::new(
+            f.span(),
+            "`#[interrupt]` function must have signature `[unsafe] fn() [-> !]`",
+        )
+        .to_compile_error()
+        .into();
+    }
+
+    if !args.is_empty() {
+        return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
+            .to_compile_error()
+            .into();
+    }
+
+    // XXX should we blacklist other attributes?
+    let attrs = f.attrs;
+    let ident = f.sig.ident;
+    let block = f.block;
+
+    #[cfg(not(feature = "v-trap"))]
+    let start_trap = proc_macro2::TokenStream::new();
+    #[cfg(feature = "v-trap")]
+    let start_trap = v_trap::start_interrupt_trap_asm(&ident, _arch);
+
+    quote!(
+        #start_trap
+        #[export_name = #ident]
+        #(#attrs)*
+        pub unsafe fn #ident() #block
+    )
+    .into()
+}
+
+#[cfg(feature = "v-trap")]
+mod v_trap {
+    use super::*;
+
+    const TRAP_SIZE: usize = 16;
+
+    #[rustfmt::skip]
+    const TRAP_FRAME: [&str; TRAP_SIZE] = [
+        "ra",
+        "t0",
+        "t1",
+        "t2",
+        "t3",
+        "t4",
+        "t5",
+        "t6",
+        "a0",
+        "a1",
+        "a2",
+        "a3",
+        "a4",
+        "a5",
+        "a6",
+        "a7",
+    ];
+
+    pub fn start_interrupt_trap_asm(
+        ident: &syn::Ident,
+        arch: RiscvArch,
+    ) -> proc_macro2::TokenStream {
+        let function = ident.to_string();
+        let (width, store, load) = match arch {
+            RiscvArch::Rv32 => (4, "sw", "lw"),
+            RiscvArch::Rv64 => (8, "sd", "ld"),
+        };
+
+        let (mut stores, mut loads) = (Vec::new(), Vec::new());
+        for (i, r) in TRAP_FRAME.iter().enumerate() {
+            stores.push(format!("        {store} {r}, {i}*{width}(sp)"));
+            loads.push(format!("        {load} {r}, {i}*{width}(sp)"));
+        }
+        let store = stores.join("\n");
+        let load = loads.join("\n");
+
+        #[cfg(feature = "s-mode")]
+        let ret = "sret";
+        #[cfg(not(feature = "s-mode"))]
+        let ret = "mret";
+
+        let instructions = format!(
+            "
+core::arch::global_asm!(
+    \".section .trap, \\\"ax\\\"
+    .align {width}
+    _start_{function}_trap:
+        addi sp, sp, - {TRAP_SIZE} * {width}
+{store}
+        call {function}
+{load}
+        addi sp, sp, {TRAP_SIZE} * {width}
+        {ret}\"
+);"
+        );
+
+        instructions.parse().unwrap()
+    }
+}

riscv-rt/src/asm.rs

@@ -245,11 +245,14 @@ _mp_hook:
 2:  li a0, 1
     ret",
     // Default implementation of `_setup_interrupts` sets the trap vector to `_start_trap`.
-    // Trap mode is set to `Direct` by default.
     // Users can override this function by defining their own `_setup_interrupts`
     ".weak _setup_interrupts
-_setup_interrupts:
-    la t0, _start_trap", // _start_trap is 16-byte aligned, so it corresponds to the Direct trap mode
+_setup_interrupts:",
+    #[cfg(not(feature = "v-trap"))]
+    "la t0, _start_trap", // _start_trap is 16-byte aligned, so it corresponds to the Direct trap mode
+    #[cfg(feature = "v-trap")]
+    "la t0, _vector_table
+    ori t0, t0, 0x1", // _vector_table is 16-byte aligned, so we must set the bit 0 to activate the Vectored trap mode
     #[cfg(feature = "s-mode")]
     "csrw stvec, t0",
     #[cfg(not(feature = "s-mode"))]
@@ -334,6 +337,38 @@ trap_handler!(
      (a0, 8), (a1, 9), (a2, 10), (a3, 11), (a4, 12), (a5, 13), (a6, 14), (a7, 15)]
 );
 
+#[cfg(feature = "v-trap")]
+cfg_global_asm!(
+    // Set the vector mode to vectored.
+    ".section .trap, \"ax\"
+    .weak _vector_table
+    .type _vector_table, @function
+    
+    .option push
+    .balign 0x100 // TODO check if this is the correct alignment
+    .option norelax
+    .option norvc
+    
+    _vector_table:
+        j _start_trap                     // Interrupt 0 is used for exceptions
+        j _start_SupervisorSoft_trap
+        j _start_trap                     // Interrupt 2 is reserved
+        j _start_MachineSoft_trap
+        j _start_trap                     // Interrupt 4 is reserved
+        j _start_SupervisorTimer_trap
+        j _start_trap                     // Interrupt 6 is reserved
+        j _start_MachineTimer_trap
+        j _start_trap                     // Interrupt 8 is reserved
+        j _start_SupervisorExternal_trap
+        j _start_trap                     // Interrupt 10 is reserved
+        j _start_MachineExternal_trap
+
+        // default table does not include the remaining interrupts.
+        // Targets with extra interrupts should override this table.
+    
+    .option pop",
+);
+
 #[rustfmt::skip]
 global_asm!(
     ".section .text.abort

riscv-rt/src/lib.rs

@@ -429,6 +429,12 @@ use riscv::register::mcause as xcause;
 
 pub use riscv_rt_macros::{entry, pre_init};
 
+#[cfg(riscv32)]
+pub use riscv_rt_macros::interrupt_riscv32 as interrupt;
+
+#[cfg(riscv64)]
+pub use riscv_rt_macros::interrupt_riscv64 as interrupt;
+
 /// We export this static with an informative name so that if an application attempts to link
 /// two copies of riscv-rt together, linking will fail. We also declare a links key in
 /// Cargo.toml which is the more modern way to solve the same problem, but we have to keep