riscv-rt: example multicore.rs could cause HART to loop forever because of race condition

[MLFlexer]

In the multicore.rs example, the other HARTs wait for an interrupt before entering main. However it seems as though there could be a race condition if HART 0 sets the interrupt flag to 1 in

riscv/riscv-rt/examples/multi_core.rs

Line 47 in 95cfb90

(addr as *mut u32).write_volatile(1);

, and then HART 1 sets it to 0 in

riscv/riscv-rt/examples/multi_core.rs

Line 19 in 95cfb90

(addr as *mut u32).write_volatile(0);

.

This would make the interrupt flag be 0, when HART 1 is entering the loop in

riscv/riscv-rt/examples/multi_core.rs

Lines 24 to 29 in 95cfb90

	loop {
	wfi();
	if mip::read().msoft() {
	break;
	}
	}

, and remain 0, because HART 0 has already set the flag, but it was overwritten by HART 1.