Open
Description
In the multicore.rs
example, the other HARTs wait for an interrupt before entering main
. However it seems as though there could be a race condition if HART 0 sets the interrupt flag to 1 in
riscv/riscv-rt/examples/multi_core.rs
Line 47 in 95cfb90
riscv/riscv-rt/examples/multi_core.rs
Line 19 in 95cfb90
This would make the interrupt flag be 0, when HART 1 is entering the loop in
riscv/riscv-rt/examples/multi_core.rs
Lines 24 to 29 in 95cfb90
Metadata
Metadata
Assignees
Labels
No labels