Accessing Arty-35T DRAM

[denishoornaert]

Hi,

I am currently trying to access the 256MB of off-chip memory (DDR) on the arty-35T.
I first started to play with the available configurations (i.e., TinyConfig in rocket-chip/src/main/scala/system/Configs.scala) by adding WithIncoherentTile() and WithDefaultMemPort() but all attempts failed.
Thereafter, I quickly realized that, unlike the VCU707, there is no AXI connection between the cores and the Arty-35T DDR controller (src/main/scala/everywhere/e300artydevkit/FPGAChip.scala).

My questions are:

• Is it really the case that the DDR controller is not mapped and thus cannot be accessed?
• Can it be mapped/accessed ? If yes, is there any known FPGA-shell (or satellite project) mapping it ?

[erikdanie]

It is accessible in the Arty100T shell, but not on the 35T shell. https://github.com/sifive/fpga-shells/blob/19d0818deda5d295154992bd4e2c490b7c905df9/src/main/scala/shell/xilinx/Arty100TShell.scala#L228
You could probably edit the code to make use of it, but this is a non-trivial task. This written with a slightly different API than the 35T uses, but you can look at the blackbox and its onboarding to see the AXI to TileLink connection that would need to be added