55#include "pal.h"
66
77/* adopt Linux x86-64 structs for FP layout: self-contained definition is needed for LibOS, so
8- * define the exact same layout with `shim_ ` prefix; taken from
8+ * define the exact same layout with `libos_ ` prefix; taken from
99 * https://elixir.bootlin.com/linux/v5.9/source/arch/x86/include/uapi/asm/sigcontext.h */
10- #define SHIM_FP_XSTATE_MAGIC1 0x46505853U
11- #define SHIM_FP_XSTATE_MAGIC2 0x46505845U
12- #define SHIM_FP_XSTATE_MAGIC2_SIZE (sizeof(SHIM_FP_XSTATE_MAGIC2 ))
13-
14- #define SHIM_XSTATE_ALIGN 64
15-
16- enum SHIM_XFEATURE {
17- SHIM_XFEATURE_FP ,
18- SHIM_XFEATURE_SSE ,
19- SHIM_XFEATURE_YMM ,
20- SHIM_XFEATURE_BNDREGS ,
21- SHIM_XFEATURE_BNDCSR ,
22- SHIM_XFEATURE_OPMASK ,
23- SHIM_XFEATURE_ZMM_Hi256 ,
24- SHIM_XFEATURE_Hi16_ZMM ,
25- SHIM_XFEATURE_PT ,
26- SHIM_XFEATURE_PKRU ,
10+ #define LIBOS_FP_XSTATE_MAGIC1 0x46505853U
11+ #define LIBOS_FP_XSTATE_MAGIC2 0x46505845U
12+ #define LIBOS_FP_XSTATE_MAGIC2_SIZE (sizeof(LIBOS_FP_XSTATE_MAGIC2 ))
13+
14+ #define LIBOS_XSTATE_ALIGN 64
15+
16+ enum LIBOS_XFEATURE {
17+ LIBOS_XFEATURE_FP ,
18+ LIBOS_XFEATURE_SSE ,
19+ LIBOS_XFEATURE_YMM ,
20+ LIBOS_XFEATURE_BNDREGS ,
21+ LIBOS_XFEATURE_BNDCSR ,
22+ LIBOS_XFEATURE_OPMASK ,
23+ LIBOS_XFEATURE_ZMM_Hi256 ,
24+ LIBOS_XFEATURE_Hi16_ZMM ,
25+ LIBOS_XFEATURE_PT ,
26+ LIBOS_XFEATURE_PKRU ,
2727};
2828
29- #define SHIM_XFEATURE_MASK_FP (1UL << SHIM_XFEATURE_FP )
30- #define SHIM_XFEATURE_MASK_SSE (1UL << SHIM_XFEATURE_SSE )
31- #define SHIM_XFEATURE_MASK_YMM (1UL << SHIM_XFEATURE_YMM )
32- #define SHIM_XFEATURE_MASK_BNDREGS (1UL << SHIM_XFEATURE_BNDREGS )
33- #define SHIM_XFEATURE_MASK_BNDCSR (1UL << SHIM_XFEATURE_BNDCSR )
34- #define SHIM_XFEATURE_MASK_OPMASK (1UL << SHIM_XFEATURE_OPMASK )
35- #define SHIM_XFEATURE_MASK_ZMM_Hi256 (1UL << SHIM_XFEATURE_ZMM_Hi256 )
36- #define SHIM_XFEATURE_MASK_Hi16_ZMM (1UL << SHIM_XFEATURE_Hi16_ZMM )
37- #define SHIM_XFEATURE_MASK_PT (1UL << SHIM_XFEATURE_PT )
38- #define SHIM_XFEATURE_MASK_PKRU (1UL << SHIM_XFEATURE_PKRU )
39-
40- #define SHIM_XFEATURE_MASK_FPSSE (SHIM_XFEATURE_MASK_FP | SHIM_XFEATURE_MASK_SSE )
41- #define SHIM_XFEATURE_MASK_AVX512 (SHIM_XFEATURE_MASK_OPMASK | SHIM_XFEATURE_MASK_ZMM_Hi256 \
42- | SHIM_XFEATURE_MASK_Hi16_ZMM )
29+ #define LIBOS_XFEATURE_MASK_FP (1UL << LIBOS_XFEATURE_FP )
30+ #define LIBOS_XFEATURE_MASK_SSE (1UL << LIBOS_XFEATURE_SSE )
31+ #define LIBOS_XFEATURE_MASK_YMM (1UL << LIBOS_XFEATURE_YMM )
32+ #define LIBOS_XFEATURE_MASK_BNDREGS (1UL << LIBOS_XFEATURE_BNDREGS )
33+ #define LIBOS_XFEATURE_MASK_BNDCSR (1UL << LIBOS_XFEATURE_BNDCSR )
34+ #define LIBOS_XFEATURE_MASK_OPMASK (1UL << LIBOS_XFEATURE_OPMASK )
35+ #define LIBOS_XFEATURE_MASK_ZMM_Hi256 (1UL << LIBOS_XFEATURE_ZMM_Hi256 )
36+ #define LIBOS_XFEATURE_MASK_Hi16_ZMM (1UL << LIBOS_XFEATURE_Hi16_ZMM )
37+ #define LIBOS_XFEATURE_MASK_PT (1UL << LIBOS_XFEATURE_PT )
38+ #define LIBOS_XFEATURE_MASK_PKRU (1UL << LIBOS_XFEATURE_PKRU )
39+
40+ #define LIBOS_XFEATURE_MASK_FPSSE (LIBOS_XFEATURE_MASK_FP | LIBOS_XFEATURE_MASK_SSE )
41+ #define LIBOS_XFEATURE_MASK_AVX512 (LIBOS_XFEATURE_MASK_OPMASK | LIBOS_XFEATURE_MASK_ZMM_Hi256 \
42+ | LIBOS_XFEATURE_MASK_Hi16_ZMM )
4343
4444/* Bytes 464..511 in the 512B layout of the FXSAVE/FXRSTOR frame are reserved for SW usage. On
4545 * CPUs supporting XSAVE/XRSTOR, these bytes are used to extend the fpstate pointer in the
4646 * sigcontext, which includes the extended state information along with fpstate information. */
47- struct shim_fpx_sw_bytes {
48- uint32_t magic1 ; /*!< SHIM_FP_XSTATE_MAGIC1 (it is an xstate context) */
49- uint32_t extended_size ; /*!< g_shim_xsave_size + SHIM_FP_STATE_MAGIC2_SIZE */
47+ struct libos_fpx_sw_bytes {
48+ uint32_t magic1 ; /*!< LIBOS_FP_XSTATE_MAGIC1 (it is an xstate context) */
49+ uint32_t extended_size ; /*!< g_libos_xsave_size + LIBOS_FP_STATE_MAGIC2_SIZE */
5050 uint64_t xfeatures ; /*!< XSAVE features (feature bit mask, including FP/SSE/extended) */
51- uint32_t xstate_size ; /*!< g_shim_xsave_size (XSAVE area size as reported by CPUID) */
51+ uint32_t xstate_size ; /*!< g_libos_xsave_size (XSAVE area size as reported by CPUID) */
5252 uint32_t padding [7 ]; /*!< for future use */
5353};
5454
5555/* 64-bit FPU frame (FXSAVE format, 512B total size) */
56- struct shim_fpstate {
56+ struct libos_fpstate {
5757 uint16_t cwd ;
5858 uint16_t swd ;
5959 uint16_t twd ;
@@ -67,76 +67,76 @@ struct shim_fpstate {
6767 uint32_t reserved2 [12 ];
6868 union {
6969 uint32_t reserved3 [12 ];
70- struct shim_fpx_sw_bytes sw_reserved ; /* potential extended state is encoded here */
70+ struct libos_fpx_sw_bytes sw_reserved ; /* potential extended state is encoded here */
7171 };
7272};
7373
74- struct shim_xstate_header {
74+ struct libos_xstate_header {
7575 uint64_t xfeatures ;
7676 uint64_t reserved1 [2 ];
7777 uint64_t reserved2 [5 ];
7878};
7979
80- struct shim_xstate {
81- struct shim_fpstate fpstate ; /* 512B legacy FXSAVE/FXRSTOR frame (FP and XMM regs) */
82- struct shim_xstate_header xstate_hdr ; /* 64B header for newer XSAVE/XRSTOR frame */
80+ struct libos_xstate {
81+ struct libos_fpstate fpstate ; /* 512B legacy FXSAVE/FXRSTOR frame (FP and XMM regs) */
82+ struct libos_xstate_header xstate_hdr ; /* 64B header for newer XSAVE/XRSTOR frame */
8383 /* rest is filled with extended regs (YMM, ZMM, ...) by HW + 4B of MAGIC2 value by SW */
84- } __attribute__((aligned (SHIM_XSTATE_ALIGN )));
84+ } __attribute__((aligned (LIBOS_XSTATE_ALIGN )));
8585
86- #define SHIM_TCB_GET (member ) \
86+ #define LIBOS_TCB_GET (member ) \
8787 ({ \
88- shim_tcb_t * tcb; \
88+ libos_tcb_t * tcb; \
8989 __typeof__(tcb->member) ret; \
9090 static_assert(sizeof(ret) == 8 || \
9191 sizeof(ret) == 4 || \
9292 sizeof(ret) == 2 || \
9393 sizeof(ret) == 1, \
94- "SHIM_TCB_GET can be used only for " \
94+ "LIBOS_TCB_GET can be used only for " \
9595 "8, 4, 2, or 1-byte(s) members"); \
9696 __asm__("mov %%gs:%c1, %0\n" \
9797 : "=r"(ret) \
9898 : "i" (offsetof(PAL_TCB, libos_tcb) + \
99- offsetof(shim_tcb_t , member)) \
99+ offsetof(libos_tcb_t , member)) \
100100 : "memory"); \
101101 ret; \
102102 })
103103
104- #define SHIM_TCB_SET (member , value ) \
104+ #define LIBOS_TCB_SET (member , value ) \
105105 do { \
106- shim_tcb_t * tcb; \
106+ libos_tcb_t * tcb; \
107107 static_assert(sizeof(tcb->member) == 8 || \
108108 sizeof(tcb->member) == 4 || \
109109 sizeof(tcb->member) == 2 || \
110110 sizeof(tcb->member) == 1, \
111- "SHIM_TCB_SET can be used only for " \
111+ "LIBOS_TCB_SET can be used only for " \
112112 "8, 4, 2, or 1-byte(s) members"); \
113113 switch (sizeof(tcb->member)) { \
114114 case 8: \
115115 __asm__("movq %0, %%gs:%c1\n" \
116116 :: "ir"(value), \
117117 "i"(offsetof(PAL_TCB, libos_tcb) + \
118- offsetof(shim_tcb_t , member)) \
118+ offsetof(libos_tcb_t , member)) \
119119 : "memory"); \
120120 break; \
121121 case 4: \
122122 __asm__("movl %0, %%gs:%c1\n" \
123123 :: "ir"(value), \
124124 "i"(offsetof(PAL_TCB, libos_tcb) + \
125- offsetof(shim_tcb_t , member)) \
125+ offsetof(libos_tcb_t , member)) \
126126 : "memory"); \
127127 break; \
128128 case 2: \
129129 __asm__("movw %0, %%gs:%c1\n" \
130130 :: "ir"(value), \
131131 "i"(offsetof(PAL_TCB, libos_tcb) + \
132- offsetof(shim_tcb_t , member)) \
132+ offsetof(libos_tcb_t , member)) \
133133 : "memory"); \
134134 break; \
135135 case 1: \
136136 __asm__("movb %0, %%gs:%c1\n" \
137137 :: "ir"(value), \
138138 "i"(offsetof(PAL_TCB, libos_tcb) + \
139- offsetof(shim_tcb_t , member)) \
139+ offsetof(libos_tcb_t , member)) \
140140 : "memory"); \
141141 break; \
142142 } \
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