Add "slide up", "slide down" intrinsics

[jhauser-us]

Assuming there are no objections, the "slide up" and "slide down" intrinsics discussed here should be added:
https://lists.riscv.org/g/tech-p-ext/topic/117971691

[topperc]

I'm not sure about the complexity of non-constant slide amounts. We need to scale the index and we need to define a behavior for out of bound slide amounts.

slide1up is a bit odd because we need to shift the element to the MSB. The programmer can synthesize this by using an insert element intrinsic and a slideup. Is there precedent from other ISAs than RVV?

I don't know about ARM. I know X86 SSE has pslldq, psrldq, and palignr for shifting whole vectors.

[jhauser-us]

We need to scale the index and we need to define a behavior for out of bound slide amounts.

I guess I never said, but I was assuming if the argument vectors are N bits (N = 32 or 64), then the shift distance in bits would be modulo N, just like an ordinary SLL or SRL. So for example, for __riscv_pslideupx_i8x4, the last argument (the number of elements to shift) would be shifted left by 3 (8 bits per element), and for RV32 this value could be fed directly to SLX.

The TG added instructions SLX and SRX for the purpose of doing such vector shifts, so it would seem odd to me not to provide XLEN-agnostic "slide up" and "slide down" intrinsics for them. Although as I said in the thread I referenced,

I would not be shocked if it were decided to limit the pslideupx and pslidedownx intrinsics to just constant shift distances.

In my view, that would be a cop-out. But I don't always win every argument.

As far as motivation, it just so happens that one of the two functions Olaf Bernstein gave as examples makes use of a vector slide or two, depending on how you code it. It's not all that rare.