Skip to content

Commit 3a68fd9

Browse files
torch2424torch2424
committed
Added a prettierrc
1 parent fb98c45 commit 3a68fd9

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

52 files changed

+834
-2391
lines changed

‎.prettierrc

+8
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,8 @@
1+
{
2+
"printWidth": 140,
3+
"singleQuote": true,
4+
"useTabs": false,
5+
"tabWidth": 2,
6+
"semi": true,
7+
"bracketSpacing": true
8+
}

‎core/cpu/cbOpcodes.ts

+37-144
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
// Imports
2-
import { Cpu } from "./index";
2+
import { Cpu } from './index';
33
import {
44
rotateRegisterLeft,
55
rotateRegisterRight,
@@ -11,14 +11,14 @@ import {
1111
shiftRightLogicalRegister,
1212
testBitOnRegister,
1313
setBitOnRegister
14-
} from "./instructions";
15-
import { concatenateBytes, performanceTimestamp } from "../helpers/index";
14+
} from './instructions';
15+
import { concatenateBytes, performanceTimestamp } from '../helpers/index';
1616
import {
1717
eightBitStoreIntoGBMemoryWithTraps,
1818
sixteenBitStoreIntoGBMemoryWithTraps,
1919
eightBitLoadFromGBMemoryWithTraps,
2020
sixteenBitLoadFromGBMemory
21-
} from "../memory/index";
21+
} from '../memory/index';
2222

2323
// Handle CB Opcodes
2424
// NOTE: Program stpes and cycles are standardized depending on the register type
@@ -57,9 +57,7 @@ export function handleCbOpcode(cbOpcode: i32): i32 {
5757
break;
5858
case 6:
5959
// Value at register HL
60-
instructionRegisterValue = <u8>eightBitLoadFromGBMemoryWithTraps(
61-
concatenateBytes(Cpu.registerH, Cpu.registerL)
62-
);
60+
instructionRegisterValue = <u8>eightBitLoadFromGBMemoryWithTraps(concatenateBytes(Cpu.registerH, Cpu.registerL));
6361
break;
6462
case 7:
6563
instructionRegisterValue = Cpu.registerA;
@@ -76,33 +74,25 @@ export function handleCbOpcode(cbOpcode: i32): i32 {
7674
if (cbOpcode <= 0x07) {
7775
// RLC register 8-bit
7876
// Z 0 0 C
79-
instructionRegisterResult = rotateRegisterLeft(
80-
instructionRegisterValue
81-
);
77+
instructionRegisterResult = rotateRegisterLeft(instructionRegisterValue);
8278
handledOpcode = true;
8379
} else if (cbOpcode <= 0x0f) {
8480
// RRC register 8-bit
8581
// Z 0 0 C
86-
instructionRegisterResult = rotateRegisterRight(
87-
instructionRegisterValue
88-
);
82+
instructionRegisterResult = rotateRegisterRight(instructionRegisterValue);
8983
handledOpcode = true;
9084
}
9185
break;
9286
case 0x01:
9387
if (cbOpcode <= 0x17) {
9488
// RL register 8-bit
9589
// Z 0 0 C
96-
instructionRegisterResult = rotateRegisterLeftThroughCarry(
97-
instructionRegisterValue
98-
);
90+
instructionRegisterResult = rotateRegisterLeftThroughCarry(instructionRegisterValue);
9991
handledOpcode = true;
10092
} else if (cbOpcode <= 0x1f) {
10193
// RR register 8-bit
10294
// Z 0 0 C
103-
instructionRegisterResult = rotateRegisterRightThroughCarry(
104-
instructionRegisterValue
105-
);
95+
instructionRegisterResult = rotateRegisterRightThroughCarry(instructionRegisterValue);
10696
handledOpcode = true;
10797
}
10898
break;
@@ -115,26 +105,20 @@ export function handleCbOpcode(cbOpcode: i32): i32 {
115105
} else if (cbOpcode <= 0x2f) {
116106
// SRA register 8-bit
117107
// Z 0 0 0
118-
instructionRegisterResult = shiftRightArithmeticRegister(
119-
instructionRegisterValue
120-
);
108+
instructionRegisterResult = shiftRightArithmeticRegister(instructionRegisterValue);
121109
handledOpcode = true;
122110
}
123111
break;
124112
case 0x03:
125113
if (cbOpcode <= 0x37) {
126114
// SWAP register 8-bit
127115
// Z 0 0 0
128-
instructionRegisterResult = swapNibblesOnRegister(
129-
instructionRegisterValue
130-
);
116+
instructionRegisterResult = swapNibblesOnRegister(instructionRegisterValue);
131117
handledOpcode = true;
132118
} else if (cbOpcode <= 0x3f) {
133119
// SRL B
134120
// Z 0 0 C
135-
instructionRegisterResult = shiftRightLogicalRegister(
136-
instructionRegisterValue
137-
);
121+
instructionRegisterResult = shiftRightLogicalRegister(instructionRegisterValue);
138122
handledOpcode = true;
139123
}
140124
break;
@@ -143,243 +127,155 @@ export function handleCbOpcode(cbOpcode: i32): i32 {
143127
// BIT 0,register 8-bit
144128
// Z 0 1 -
145129
//TODO: Optimize this not to do logic of setting register back
146-
instructionRegisterResult = testBitOnRegister(
147-
0,
148-
instructionRegisterValue
149-
);
130+
instructionRegisterResult = testBitOnRegister(0, instructionRegisterValue);
150131
handledOpcode = true;
151132
} else if (cbOpcode <= 0x4f) {
152133
// BIT 1,register 8-bit
153134
// Z 0 1 -
154-
instructionRegisterResult = testBitOnRegister(
155-
1,
156-
instructionRegisterValue
157-
);
135+
instructionRegisterResult = testBitOnRegister(1, instructionRegisterValue);
158136
handledOpcode = true;
159137
}
160138
break;
161139
case 0x05:
162140
if (cbOpcode <= 0x57) {
163141
// BIT 2,register 8-bit
164142
// Z 0 1 -
165-
instructionRegisterResult = testBitOnRegister(
166-
2,
167-
instructionRegisterValue
168-
);
143+
instructionRegisterResult = testBitOnRegister(2, instructionRegisterValue);
169144
handledOpcode = true;
170145
} else if (cbOpcode <= 0x5f) {
171146
// BIT 3,register 8-bit
172147
// Z 0 1 -
173-
instructionRegisterResult = testBitOnRegister(
174-
3,
175-
instructionRegisterValue
176-
);
148+
instructionRegisterResult = testBitOnRegister(3, instructionRegisterValue);
177149
handledOpcode = true;
178150
}
179151
break;
180152
case 0x06:
181153
if (cbOpcode <= 0x67) {
182154
// BIT 4,register 8-bit
183155
// Z 0 1 -
184-
instructionRegisterResult = testBitOnRegister(
185-
4,
186-
instructionRegisterValue
187-
);
156+
instructionRegisterResult = testBitOnRegister(4, instructionRegisterValue);
188157
handledOpcode = true;
189158
} else if (cbOpcode <= 0x6f) {
190159
// BIT 5,register 8-bit
191160
// Z 0 1 -
192-
instructionRegisterResult = testBitOnRegister(
193-
5,
194-
instructionRegisterValue
195-
);
161+
instructionRegisterResult = testBitOnRegister(5, instructionRegisterValue);
196162
handledOpcode = true;
197163
}
198164
break;
199165
case 0x07:
200166
if (cbOpcode <= 0x77) {
201167
// BIT 6,register 8-bit
202168
// Z 0 1 -
203-
instructionRegisterResult = testBitOnRegister(
204-
6,
205-
instructionRegisterValue
206-
);
169+
instructionRegisterResult = testBitOnRegister(6, instructionRegisterValue);
207170
handledOpcode = true;
208171
} else if (cbOpcode <= 0x7f) {
209172
// BIT 7,register 8-bit
210173
// Z 0 1 -
211-
instructionRegisterResult = testBitOnRegister(
212-
7,
213-
instructionRegisterValue
214-
);
174+
instructionRegisterResult = testBitOnRegister(7, instructionRegisterValue);
215175
handledOpcode = true;
216176
}
217177
break;
218178
case 0x08:
219179
if (cbOpcode <= 0x87) {
220180
// Res 0,register 8-bit
221181
// - - - -
222-
instructionRegisterResult = setBitOnRegister(
223-
0,
224-
0,
225-
instructionRegisterValue
226-
);
182+
instructionRegisterResult = setBitOnRegister(0, 0, instructionRegisterValue);
227183
handledOpcode = true;
228184
} else if (cbOpcode <= 0x8f) {
229185
// Res 1,register 8-bit
230186
// - - - -
231-
instructionRegisterResult = setBitOnRegister(
232-
1,
233-
0,
234-
instructionRegisterValue
235-
);
187+
instructionRegisterResult = setBitOnRegister(1, 0, instructionRegisterValue);
236188
handledOpcode = true;
237189
}
238190
break;
239191
case 0x09:
240192
if (cbOpcode <= 0x97) {
241193
// Res 2,register 8-bit
242194
// - - - -
243-
instructionRegisterResult = setBitOnRegister(
244-
2,
245-
0,
246-
instructionRegisterValue
247-
);
195+
instructionRegisterResult = setBitOnRegister(2, 0, instructionRegisterValue);
248196
handledOpcode = true;
249197
} else if (cbOpcode <= 0x9f) {
250198
// Res 3,register 8-bit
251199
// - - - -
252-
instructionRegisterResult = setBitOnRegister(
253-
3,
254-
0,
255-
instructionRegisterValue
256-
);
200+
instructionRegisterResult = setBitOnRegister(3, 0, instructionRegisterValue);
257201
handledOpcode = true;
258202
}
259203
break;
260204
case 0x0a:
261205
if (cbOpcode <= 0xa7) {
262206
// Res 4,register 8-bit
263207
// - - - -
264-
instructionRegisterResult = setBitOnRegister(
265-
4,
266-
0,
267-
instructionRegisterValue
268-
);
208+
instructionRegisterResult = setBitOnRegister(4, 0, instructionRegisterValue);
269209
handledOpcode = true;
270210
} else if (cbOpcode <= 0xaf) {
271211
// Res 5,register 8-bit
272212
// - - - -
273-
instructionRegisterResult = setBitOnRegister(
274-
5,
275-
0,
276-
instructionRegisterValue
277-
);
213+
instructionRegisterResult = setBitOnRegister(5, 0, instructionRegisterValue);
278214
handledOpcode = true;
279215
}
280216
break;
281217
case 0x0b:
282218
if (cbOpcode <= 0xb7) {
283219
// Res 6,register 8-bit
284220
// - - - -
285-
instructionRegisterResult = setBitOnRegister(
286-
6,
287-
0,
288-
instructionRegisterValue
289-
);
221+
instructionRegisterResult = setBitOnRegister(6, 0, instructionRegisterValue);
290222
handledOpcode = true;
291223
} else if (cbOpcode <= 0xbf) {
292224
// Res 7,register 8-bit
293225
// - - - -
294-
instructionRegisterResult = setBitOnRegister(
295-
7,
296-
0,
297-
instructionRegisterValue
298-
);
226+
instructionRegisterResult = setBitOnRegister(7, 0, instructionRegisterValue);
299227
handledOpcode = true;
300228
}
301229
break;
302230
case 0x0c:
303231
if (cbOpcode <= 0xc7) {
304232
// SET 0,register 8-bit
305233
// - - - -
306-
instructionRegisterResult = setBitOnRegister(
307-
0,
308-
1,
309-
instructionRegisterValue
310-
);
234+
instructionRegisterResult = setBitOnRegister(0, 1, instructionRegisterValue);
311235
handledOpcode = true;
312236
} else if (cbOpcode <= 0xcf) {
313237
// SET 1,register 8-bit
314238
// - - - -
315-
instructionRegisterResult = setBitOnRegister(
316-
1,
317-
1,
318-
instructionRegisterValue
319-
);
239+
instructionRegisterResult = setBitOnRegister(1, 1, instructionRegisterValue);
320240
handledOpcode = true;
321241
}
322242
break;
323243
case 0x0d:
324244
if (cbOpcode <= 0xd7) {
325245
// SET 2,register 8-bit
326246
// - - - -
327-
instructionRegisterResult = setBitOnRegister(
328-
2,
329-
1,
330-
instructionRegisterValue
331-
);
247+
instructionRegisterResult = setBitOnRegister(2, 1, instructionRegisterValue);
332248
handledOpcode = true;
333249
} else if (cbOpcode <= 0xdf) {
334250
// SET 3,register 8-bit
335251
// - - - -
336-
instructionRegisterResult = setBitOnRegister(
337-
3,
338-
1,
339-
instructionRegisterValue
340-
);
252+
instructionRegisterResult = setBitOnRegister(3, 1, instructionRegisterValue);
341253
handledOpcode = true;
342254
}
343255
break;
344256
case 0x0e:
345257
if (cbOpcode <= 0xe7) {
346258
// SET 4,register 8-bit
347259
// - - - -
348-
instructionRegisterResult = setBitOnRegister(
349-
4,
350-
1,
351-
instructionRegisterValue
352-
);
260+
instructionRegisterResult = setBitOnRegister(4, 1, instructionRegisterValue);
353261
handledOpcode = true;
354262
} else if (cbOpcode <= 0xef) {
355263
// SET 5,register 8-bit
356264
// - - - -
357-
instructionRegisterResult = setBitOnRegister(
358-
5,
359-
1,
360-
instructionRegisterValue
361-
);
265+
instructionRegisterResult = setBitOnRegister(5, 1, instructionRegisterValue);
362266
handledOpcode = true;
363267
}
364268
break;
365269
case 0x0f:
366270
if (cbOpcode <= 0xf7) {
367271
// SET 6,register 8-bit
368272
// - - - -
369-
instructionRegisterResult = setBitOnRegister(
370-
6,
371-
1,
372-
instructionRegisterValue
373-
);
273+
instructionRegisterResult = setBitOnRegister(6, 1, instructionRegisterValue);
374274
handledOpcode = true;
375275
} else if (cbOpcode <= 0xff) {
376276
// SET 7,register 8-bit
377277
// - - - -
378-
instructionRegisterResult = setBitOnRegister(
379-
7,
380-
1,
381-
instructionRegisterValue
382-
);
278+
instructionRegisterResult = setBitOnRegister(7, 1, instructionRegisterValue);
383279
handledOpcode = true;
384280
}
385281
break;
@@ -407,10 +303,7 @@ export function handleCbOpcode(cbOpcode: i32): i32 {
407303
break;
408304
case 6:
409305
// Value at register HL
410-
eightBitStoreIntoGBMemoryWithTraps(
411-
concatenateBytes(Cpu.registerH, Cpu.registerL),
412-
instructionRegisterResult
413-
);
306+
eightBitStoreIntoGBMemoryWithTraps(concatenateBytes(Cpu.registerH, Cpu.registerL), instructionRegisterResult);
414307
break;
415308
case 7:
416309
Cpu.registerA = instructionRegisterResult;

0 commit comments

Comments
 (0)