Initial files

Author: petewarden

Diff for: .gitignore

@@ -0,0 +1 @@
+gen

Diff for: Makefile

@@ -0,0 +1,80 @@
+# Makefile for all the examples in the STM32 Bare Library.
+
+# Override this if you want to store temporary files outside of the source folder.
+GENDIR := ./gen/
+
+# Sub-directories holding generated files.
+OBJDIR := $(GENDIR)/obj/
+ELFDIR := $(GENDIR)/elf/
+BINDIR := $(GENDIR)/bin/
+
+# The cross-compilation toolchain prefix to use for gcc binaries.
+CROSS_PREFIX := arm-none-eabi
+AS := $(CROSS_PREFIX)-as
+CC := $(CROSS_PREFIX)-gcc
+LD := $(CROSS_PREFIX)-ld.bfd
+OBJCOPY := $(CROSS_PREFIX)-objcopy
+
+# Debug symbols are enabled with -g, but since we compile ELFs down to bin files, these don't
+# affect the code size on-device.
+CCFLAGS := -mcpu=cortex-m3 -mthumb -g
+
+# We rely on headers from Arm's CMSIS library for things like device register layouts. To
+# download the library, use `git clone https://github.com/ARM-software/CMSIS_5` in the parent
+# folder of the one this Makefile is in (not this folder, but the one above).
+CMSIS_DIR :=../CMSIS_5/
+ifeq ($(shell test -d $(CMSIS_DIR) ; echo $$?), 1)
+  $(error "CMSIS not found at '$(CMSIS_DIR)' - try 'git clone https://github.com/ARM-software/CMSIS_5 $(CMSIS_DIR)'")
+endif
+
+# Allow CMSIS core headers, and ones from this library.
+INCLUDES := \
+-isystem$(CMSIS_DIR)/CMSIS/Core/Include/ \
+-I./include 
+
+ASFLAGS :=
+
+# Defines the offsets used when linking binaries for the STM32.
+LDFLAGS := -T stm32_linker_layout.lds
+
+# Rule used when no target is specified.
+all: $(BINDIR)/examples/blink.bin $(BINDIR)/examples/hello_world.bin
+
+clean:
+	rm -rf $(GENDIR)
+
+# Generic rules for generating different file types.
+$(OBJDIR)%.o: %.c
+	@mkdir -p $(dir $@)
+	$(CC) $(CCFLAGS) $(INCLUDES) -c $< -o $@
+
+$(OBJDIR)%.o: %.s
+	@mkdir -p $(dir $@)
+	$(AS) $(ASFLAGS) $< -o $@
+
+$(BINDIR)/%.bin: $(ELFDIR)/%.elf
+	@mkdir -p $(dir $@)
+	$(OBJCOPY) $< $@ -O binary
+
+# Blink example rules.
+# The boot.s file need to be first in linking order, since it has to be at the start of
+# flash memory when the chip is reset.
+BLINK_SRCS := source/boot.s \
+$(wildcard examples/blink/*.c)
+BLINK_OBJS := $(addprefix $(OBJDIR), \
+$(patsubst %.c,%.o,$(patsubst %.s,%.o,$(BLINK_SRCS))))
+
+# Link the blink example.
+$(ELFDIR)/examples/blink.elf: $(BLINK_OBJS)
+	@mkdir -p $(dir $@)
+	$(LD) $(LDFLAGS) -o $@ $(BLINK_OBJS)
+
+# Hello world example rules.
+HELLO_WORLD_SRCS := source/boot.s \
+$(wildcard examples/hello_world/*.c)
+HELLO_WORLD_OBJS := $(addprefix $(OBJDIR), \
+$(patsubst %.c,%.o,$(patsubst %.s,%.o,$(HELLO_WORLD_SRCS))))
+
+$(ELFDIR)/examples/hello_world.elf: $(HELLO_WORLD_OBJS)
+	@mkdir -p $(dir $@)
+	$(LD) $(LDFLAGS) -o $@ $(HELLO_WORLD_OBJS)

Diff for: README.md

@@ -0,0 +1 @@
+git clone https://github.com/ARM-software/CMSIS_5

Diff for: examples/blink/blink_main.c

@@ -0,0 +1,34 @@
+/* Copyright 2017 Pete Warden. All Rights Reserved.
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+    http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// This example shows how to write a minimal "Blue Pill" program that blinks the
+// LED continuously.
+
+#include "led.h"
+#include "timers.h"
+
+// You need a function named "OnReset" in your program to act like "main" in
+// traditional C. This will be called when the processor starts up.
+void OnReset(void) {
+  // Before the LED can be accessed, the device registers need to be set up.
+  LedInit();
+  // We'll keep looping forever, turning the LED on and off.
+  while (1) {
+    LedOn();
+    // This delay function is inefficient because it has the processor spin in
+    // a loop executing no-ops, rather than going to sleep and saving power.
+    // It's simpler to call though, so we'll use it for this example.
+    BusyWaitMicroseconds(200 * 1000);
+    LedOff();
+    BusyWaitMicroseconds(200 * 1000);
+  }
+}

Diff for: examples/hello_world/hello_world_main.c

@@ -0,0 +1,25 @@
+/* Copyright 2017 Pete Warden. All Rights Reserved.
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+    http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// An example of writing a string to a connected debug system using Arm's
+// semihosting system. If you have openocd running and 'arm semihosting enable'
+// has been run, you should see "Hello World!" in the openocd console logs.
+
+#include "debug_log.h"
+
+// The function that's called when the chip is started.
+void OnReset(void) {
+  // Output "Hello World!" to the OpenOCD console.
+  // This call can take hundreds of milliseconds, so don't use it in
+  // performance-critical code!
+  DebugLog("Hello World!\n");
+}

Diff for: include/core_stm32.h

@@ -0,0 +1,109 @@
+/* Copyright 2017 Pete Warden. All Rights Reserved.
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+    http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// Provides useful definitions for processor-specific parts of the STM32
+// platform, such as device register locations.
+
+#ifndef INCLUDE_CORE_STM32_H
+#define INCLUDE_CORE_STM32_H
+
+// We need a couple of STM32-specific definitions before we include the main M3
+// header file.
+typedef enum IRQn {
+  NonMaskableInt_IRQn = -14,
+  MemoryManagement_IRQn = -12,
+  BusFault_IRQn = -11,
+  UsageFault_IRQn = -10,
+  SVCall_IRQn = -5,
+  DebugMonitor_IRQn = -4,
+  PendSV_IRQn = -2,
+  SysTick_IRQn = -1,
+  WWDG_IRQn = 0,
+  PVD_IRQn = 1,
+  TAMPER_IRQn = 2,
+  RTC_IRQn = 3,
+  FLASH_IRQn = 4,
+  RCC_IRQn = 5,
+  EXTI0_IRQn = 6,
+  EXTI1_IRQn = 7,
+  EXTI2_IRQn = 8,
+  EXTI3_IRQn = 9,
+  EXTI4_IRQn = 10,
+  DMA1_Channel1_IRQn = 11,
+  DMA1_Channel2_IRQn = 12,
+  DMA1_Channel3_IRQn = 13,
+  DMA1_Channel4_IRQn = 14,
+  DMA1_Channel5_IRQn = 15,
+  DMA1_Channel6_IRQn = 16,
+  DMA1_Channel7_IRQn = 17,
+} IRQn_Type;
+#define __NVIC_PRIO_BITS 4
+
+// This include relies on CMSIS being downloaded. See README for details.
+#include <core_cm3.h>
+
+// Now define some device-specific structures. For more information, see
+// http://www.st.com/content/ccc/resource/technical/document/reference_manual/59/b9/ba/7f/11/af/43/d5/CD00171190.pdf/files/CD00171190.pdf/jcr:content/translations/en.CD00171190.pdf
+
+// Reset and Clock Control Layout.
+typedef struct {
+  __IO uint32_t CR;        // Clock Control.
+  __IO uint32_t CFGR;      // Clock Configuration #1.
+  __IO uint32_t CIR;       // Clock Interrupt.
+  __IO uint32_t APB2RSTR;  // APB2 Peripheral Reset.
+  __IO uint32_t APB1RSTR;  // APB1 Peripheral Reset.
+  __IO uint32_t AHBENR;    // AHB Peripheral Clock.
+  __IO uint32_t APB2ENR;   // APB2 Peripheral Clock Enable.
+  __IO uint32_t APB1ENR;   // APB1 Peripheral Clock Enable.
+  __IO uint32_t BDCR;      // Backup Domain Control.
+  __IO uint32_t CSR;       // Clock Control and status.
+  __IO uint32_t AHBRSTR;   // AHB Peripheral Reset.
+  __IO uint32_t CFGR2;     // Clock Configuration #2.
+  __IO uint32_t CFGR3;     // Clock Configuration #3.
+} RCC_t;
+
+// GPIO Control Layout.
+typedef struct {
+  __IO uint32_t CRL;      // Control Low.
+  __IO uint32_t CRH;      // Control High.
+  __IO uint16_t IDR;      // Port Input Data.
+  __IO uint16_t UNUSED1;  // Unused.
+  __IO uint16_t ODR;      // Output data register.
+  __IO uint16_t UNUSED2;  // Unused.
+  __IO uint32_t BSRR;     // Port Bit Set/Reset.
+  __IO uint16_t BRR;      // Bit Reset.
+  __IO uint16_t UNUSED3;  // Unused.
+  __IO uint32_t LCKR;     // Port Configuration Lock.
+} GPIO_t;
+
+// Addresses of peripherals.
+#define RCC_BASE ((uint32_t)0x40021000)
+#define GPIOA_BASE ((uint32_t)0x40010800)
+#define GPIOB_BASE ((uint32_t)0x40010C00)
+#define GPIOC_BASE ((uint32_t)0x40011000)
+
+// Globals for accessing peripherals.
+#define RCC ((RCC_t*)RCC_BASE)
+#define GPIOA ((GPIO_t*)GPIOA_BASE)
+#define GPIOB ((GPIO_t*)GPIOB_BASE)
+#define GPIOC ((GPIO_t*)GPIOC_BASE)
+
+// Register access values.
+#define RCC_GPIOA_ENABLE (0x04)
+#define RCC_GPIOB_ENABLE (0x08)
+#define RCC_GPIOC_ENABLE (0x10)
+
+#define GPIO_MODE_OUT_2 (0x02)
+#define GPIO_CONF_GP_UD (0x0)
+#define GPIO_CONF_GP_OD (0x4)
+
+#endif  // INCLUDE_CORE_STM32_H

Diff for: include/debug_log.h

@@ -0,0 +1,31 @@
+/* Copyright 2017 Pete Warden. All Rights Reserved.
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+    http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// Output strings to a debug console, using semihosting.
+// You'll need to enable this option in the OpenOCD configuration using:
+// arm semihosting enable
+
+#ifndef INCLUDE_DEBUG_LOG_H
+#define INCLUDE_DEBUG_LOG_H
+
+// Writes a string to the OpenOCD debug console. This can take hundreds of
+// milliseconds, so don't call this in performance-intensive code.
+static inline void DebugLog(char* s) {
+  asm("mov r0, #0x04\n" // SYS_WRITE0
+      "mov r1, %[str]\n"
+      "bkpt #0xAB\n"
+      :
+      : [str] "r"(s)
+      : "r0", "r1");
+}
+
+#endif  // INCLUDE_DEBUG_LOG_H

Diff for: include/led.h

@@ -0,0 +1,39 @@
+/* Copyright 2017 Pete Warden. All Rights Reserved.
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+    http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// Control the LED on a "Blue Pill" STM32-compatible board.
+
+#ifndef INCLUDE_LED_H
+#define INCLUDE_LED_H
+
+#include "core_stm32.h"
+
+// Known location of the LED on the "Blue Pill" STM32 SoCs.
+#define LED_PORT (13)
+
+// This needs to be called before the LED can be accessed.
+static inline void LedInit() {
+  // Enable GPIOC.
+  RCC->APB2ENR |= RCC_GPIOC_ENABLE;
+
+  // Set up speed and configuration.
+  const int shift = (LED_PORT - 8) * 4;
+  const uint32_t old_config = GPIOC->CRH;
+  const uint32_t cleared_config = (old_config & ~(0xf << shift));
+  GPIOC->CRH = cleared_config | ((GPIO_MODE_OUT_2 | GPIO_CONF_GP_OD) << shift);
+}
+
+// LedInit() must be called before these will work.
+static inline void LedOn() { GPIOC->BSRR = (1 << (LED_PORT + 16)); }
+static inline void LedOff() { GPIOC->BSRR = (1 << LED_PORT); }
+
+#endif  // INCLUDE_LED_H

Diff for: include/timers.h

@@ -0,0 +1,30 @@
+/* Copyright 2017 Pete Warden. All Rights Reserved.
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+    http://www.apache.org/licenses/LICENSE-2.0
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+// Timer utilities for the "Blue Pill" STM32 board.
+
+#ifndef INCLUDE_TIMERS_H
+#define INCLUDE_TIMERS_H
+
+#include <stdint.h>
+
+// Spin in a loop for roughly the specified number of microseconds. This is
+// using instruction timing, so it's not precise, and the processor will be
+// consuming power while this is running.
+static inline void BusyWaitMicroseconds(int32_t us) {
+  // Each loop takes very roughly one microsecond on a Blue Pill.
+  volatile int32_t count = us;
+  for (; count > 0; --count)
+    ;
+}
+
+#endif  // INCLUDE_TIMERS_H