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Commit d7dd352

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wangyang
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riscv: keep mstatus.MPP=M after mret on harts without U-mode
1 parent 938efd1 commit d7dd352

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Lines changed: 2 additions & 1 deletion

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qemu/target/riscv/op_helper.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,8 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb)
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MSTATUS_MIE : MSTATUS_UIE << prev_priv,
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get_field(mstatus, MSTATUS_MPIE));
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mstatus = set_field(mstatus, MSTATUS_MPIE, 1);
152-
mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U);
152+
mstatus = set_field(mstatus, MSTATUS_MPP,
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riscv_has_ext(env, RVU) ? PRV_U : PRV_M);
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#ifdef TARGET_RISCV32
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env->mstatush = set_field(env->mstatush, MSTATUS_MPV, 0);
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#else

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