[#2389] test: cover D-width atomic gate

Author: carlosqwqqwq

tests/unit/test_riscv.c

@@ -55,6 +55,29 @@ static void test_riscv64_nop(void)
     OK(uc_close(uc));
 }
 
+static void test_riscv64_dwidth_atomic_without_a(void)
+{
+    uc_engine *uc;
+    const char code[] = "\x2f\xb5\x05\x10"; // lr.d a0, (a1)
+    uint64_t misa;
+    uint64_t address = 0x2000;
+    uint64_t value = 0;
+
+    OK(uc_open(UC_ARCH_RISCV, UC_MODE_RISCV64, &uc));
+    OK(uc_mem_map(uc, code_start, code_len, UC_PROT_ALL));
+    OK(uc_mem_write(uc, code_start, code, sizeof(code) - 1));
+    OK(uc_mem_write(uc, address, &value, sizeof(value)));
+    OK(uc_reg_read(uc, UC_RISCV_REG_MISA, &misa));
+    misa &= ~1ULL;
+    OK(uc_reg_write(uc, UC_RISCV_REG_MISA, &misa));
+    OK(uc_reg_write(uc, UC_RISCV_REG_A1, &address));
+
+    uc_assert_err(UC_ERR_EXCEPTION,
+                  uc_emu_start(uc, code_start,
+                                code_start + sizeof(code) - 1, 0, 0));
+    OK(uc_close(uc));
+}
+
 static void test_riscv32_until_pc_update(void)
 {
     uc_engine *uc;
@@ -911,6 +934,8 @@ static void test_riscv_priv(void)
 TEST_LIST = {
     {"test_riscv32_nop", test_riscv32_nop},
     {"test_riscv64_nop", test_riscv64_nop},
+    {"test_riscv64_dwidth_atomic_without_a",
+     test_riscv64_dwidth_atomic_without_a},
     {"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update},
     {"test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update},
     {"test_riscv64_until_at_page_end", test_riscv64_until_at_page_end},