RISC-V: D-width atomic instructions retire on harts without the A extension

[carlosqwqqwq]

RISC-V: D-width atomic instructions retire without the A extension

Rechecked revision

The report was rechecked against the public Unicorn dev branch at
938efd13aeab73155f31cf707a2094c6ccaa36dd.

Problem

The eleven RV64 D-width atomic translators omit the A-extension gate used by
their W-width siblings. On a hart without A, lr.d, sc.d, and amo*.d
therefore retire and may perform memory effects instead of trapping.

Public reproducer

The witness, controls, and the explicit A-clear riscv_any build-profile patch
are available at
https://github.com/carlosqwqqwq/unicorn-riscv-repros/tree/main/u030.
Apply patches/no-a-any.patch to a clean public Unicorn checkout, build it,
set LIBUNICORN_PATH to that build, and run u030/run.sh. The D-width
witness must trap; the W-width control must retain its existing trap behavior.
The profile patch is public and only constructs the no-A test configuration;
it does not hide any source change used by the report.

Expected behavior

Every LR/SC/AMO encoding requires A unless another explicitly supported
extension owns that operation. A-enabled models remain legal.

Root cause and proposed fix

Add REQUIRE_EXT(ctx, RVA); to each D-width atomic translator before its
memory helper runs. The change is included in PR #2395.