add doxygen comments

Author: soheilshahrouz

libs/libarchfpga/src/physical_types.h

@@ -1532,22 +1532,21 @@ struct t_pb_graph_pin_power {
 /* FPGA Routing architecture                                                                     */
 /*************************************************************************************************/
 
-/* Description of routing channel distribution across the FPGA, only available for global routing
- * Width is standard dev. for Gaussian.  xpeak is where peak     *
- * occurs. dc is the dc offset for Gaussian and pulse waveforms. */
+/// @brief Description of routing channel distribution across the FPGA, only available for global routing
 enum class e_stat {
     UNIFORM,
     GAUSSIAN,
     PULSE,
     DELTA
 };
 
+/// @brief Parameters describing a channel distribution.
 struct t_chan {
-    e_stat type;
-    float peak;
-    float width;
-    float xpeak;
-    float dc;
+    e_stat type;  ///< Distribution type
+    float peak;   ///< Peak value
+    float width;  ///< Standard deviation (Gaussian)
+    float xpeak;  ///< Peak location (Gaussian)
+    float dc;     ///< DC offset (Gaussian, pulse)
 };
 
 /* chan_x_dist: Describes the x-directed channel width distribution.         *
@@ -1754,13 +1753,14 @@ struct t_hash_segment_inf {
     }
 };
 
+/// @brief Enumerates switch types used in the FPGA architecture and RR graph.
 enum class e_switch_type {
-    MUX = 0,   //A configurable (buffered) mux (single-driver)
-    TRISTATE,  //A configurable tristate-able buffer (multi-driver)
-    PASS_GATE, //A configurable pass transistor switch (multi-driver)
-    SHORT,     //A non-configurable electrically shorted connection (multi-driver)
-    BUFFER,    //A non-configurable non-tristate-able buffer (uni-driver)
-    INVALID,   //Unspecified, usually an error
+    MUX = 0,   ///< A configurable (buffered) mux (single-driver)
+    TRISTATE,  ///< A configurable tristate-able buffer (multi-driver)
+    PASS_GATE, ///< A configurable pass transistor switch (multi-driver)
+    SHORT,     ///< A non-configurable electrically shorted connection (multi-driver)
+    BUFFER,    ///< A non-configurable non-tristate-able buffer (uni-driver)
+    INVALID,   ///< Unspecified, usually an error
     NUM_SWITCH_TYPES
 };
 

vpr/src/route/rr_graph_generation/rr_graph_switch_utils.h

@@ -1,6 +1,21 @@
 
 #pragma once
 
+/**
+ * @file
+ * @brief Utilities for creating and initializing rr_switch structures from architecture switches.
+ *
+ * This header defines functions that translate high-level architecture switch
+ * descriptions (`t_arch_switch_inf`) into detailed rr_switch items used in RR graph.
+ * These functions:
+ *   - Copy and resolve switch electrical parameters into `t_rr_switch_inf`.
+ *   - Expand architecture switches into fanin-specific rr_switch variants.
+ *   - Provide mappings from (arch_switch, fanin) --> rr_switch index.
+ *
+ * They are invoked during RR graph construction to allocate, initialize,
+ * and remap all switch information.
+ */
+
 #include <map>
 #include <vector>
 

vpr/src/route/rr_graph_generation/rr_graph_tile_nodes.cpp

@@ -12,7 +12,7 @@ void add_classes_rr_graph(RRGraphBuilder& rr_graph_builder,
                           const std::vector<int>& class_num_vec,
                           const t_physical_tile_loc& root_loc,
                           t_physical_tile_type_ptr physical_type) {
-    auto& mutable_device_ctx = g_vpr_ctx.mutable_device();
+    DeviceContext& mutable_device_ctx = g_vpr_ctx.mutable_device();
 
     for (int class_num : class_num_vec) {
         e_pin_type class_type = get_class_type_from_class_physical_num(physical_type, class_num);
@@ -106,7 +106,7 @@ void connect_src_sink_to_pins(RRGraphBuilder& rr_graph_builder,
                               bool switches_remapped) {
     for (int class_num : class_num_vec) {
         const std::vector<int>& pin_list = get_pin_list_from_class_physical_num(physical_type_ptr, class_num);
-        auto class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num);
+        e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num);
         RRNodeId class_rr_node_id = get_class_rr_node_id(rr_graph_builder.node_lookup(), physical_type_ptr, tile_loc, class_num);
         VTR_ASSERT(class_rr_node_id != RRNodeId::INVALID());
         for (int pin_num : pin_list) {

vpr/src/route/rr_graph_generation/rr_graph_tile_nodes.h

@@ -1,17 +1,29 @@
 
 #pragma once
 
+/**
+ * @file
+ * @brief Functions for creating RR graph nodes for tile classes and pins.
+ *
+ * This header declares utilities used during RR graph construction:
+ * - Adds SOURCE and SINK nodes for within a tile.
+ * - Adds OPIN and IPIN nodes for physical pins of a tile.
+ * - Provides connections between source/sinks and pins using delayless switches.
+ */
+
 #include <vector>
 #include "physical_types.h"
 #include "rr_edge.h"
 
 class RRGraphBuilder;
 
+/// @brief Create SOURCE and SINK nodes for each class in a tile and set their properties.
 void add_classes_rr_graph(RRGraphBuilder& rr_graph_builder,
                           const std::vector<int>& class_num_vec,
                           const t_physical_tile_loc& root_loc,
                           t_physical_tile_type_ptr physical_type);
 
+/// @brief Create OPIN and IPIN nodes for each pin in a tile and set their properties.
 void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder,
                        const std::vector<int>& pin_num_vec,
                        const t_physical_tile_loc& root_loc,