Fix indentation of generate blocks omitting keyword (#1820).

* verilog-mode.el (verilog-in-generate-region-p):
Fix indentation of generate blocks omitting keyword.
Revert changes of PR #1815 and update tests accordingly.

Signed-off-by: Gonzalo Larumbe <[email protected]>

Author: gmlarumbe

tests/indent_generate.v

@@ -1,15 +1,31 @@
 module test();
-   
+
   reg [3:0] x;
- 
+
   genvar    i;
   generate
   for(i=0; i<4; i=i+1) begin:a
   always @(*) begin
   x[i] = 1;
   end
-  wire y = 0; 
+  wire y = 0;
   end
   endgenerate
 endmodule // test
 
+
+module test();
+
+  reg [3:0] x;
+
+  genvar    i;
+
+  for(i=0; i<4; i=i+1) begin:a
+  always @(*) begin
+  x[i] = 1;
+  end
+  wire y = 0;
+  end
+
+endmodule // test
+

tests/indent_generate_bug1257.v

@@ -0,0 +1,97 @@
+// Issue #1257
+
+module t1
+ (
+ );
+
+genvar pipe;
+logic [1:0] v;
+logic x;
+
+//generate
+for (pipe=0; pipe<2; pipe++) begin : v_bl
+     always_comb begin
+         assign v[pipe] = '0;
+     end
+     assign x = '0;  // will be incorrectly indented to column 0
+end
+//endgenerate
+
+endmodule
+
+
+
+
+module indent;
+
+    // CASE 1 indented wrong.  See end of module
+    for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
+       for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
+          if (`asdf [aa]) begin : gen_jj
+
+             always_ff @ (negedge cc [aa][bb]) begin
+                if (dd [aa][bb])) begin
+                   for (uint_t d_idx = 0; d_idx < 16; d_idx++)
+                     ee [aa][bb].push_front (tx_dfe_out [aa][bb]  [15 - d_idx]);
+                end
+             end
+
+    always_ff @ (posedge hs_clk) begin
+       ee_size [aa][bb] = ee [aa][bb].size();
+       if (ee_size [aa][bb] > 0)
+         gg [aa][bb] <= ee [aa][bb].pop_front;
+    end
+
+end : gen_jj
+       end : gen_ii
+    end : gen_hh
+
+
+
+    // this indents correctly without generate/endgenerate
+    for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
+       for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
+          if (`asdf [aa]) begin : gen_jj
+             assign a[aa][bb] = aa + bb;
+             assign b[aa][bb] = aa + bb;
+          end : gen_jj
+       end : gen_ii
+    end : gen_hh
+
+
+    // this works now with gen/endgen
+    generate
+       for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
+          for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
+             always @ (negedge cc)
+               a = 5;
+             always @ (negedge dd)
+               w = 2;
+          end : gen_ii
+       end : gen_hh
+    endgenerate
+
+
+    // CASE 1 again. No change but works - apparently since verilog-mode hit a generate statement above this line
+    for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
+       for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
+          if (`asdf [aa]) begin : gen_jj
+
+             always_ff @ (negedge cc [aa][bb]) begin
+                if (dd [aa][bb])) begin
+                   for (uint_t d_idx = 0; d_idx < 16; d_idx++)
+                     ee [aa][bb].push_front (tx_dfe_out [aa][bb]  [15 - d_idx]);
+                end
+             end
+
+             always_ff @ (posedge hs_clk) begin
+                ee_size [aa][bb] = ee [aa][bb].size();
+                if (ee_size [aa][bb] > 0)
+                  gg [aa][bb] <= ee [aa][bb].pop_front;
+             end
+
+          end : gen_jj
+       end : gen_ii
+    end : gen_hh
+
+endmodule : indent

tests/indent_generate_bug1404.sv

@@ -6,7 +6,6 @@ module test
     (input logic y,z;
     );
 
-generate
     if (OPT = 1) begin
        always_comb begin
           y = 1'b1;
@@ -22,6 +21,5 @@ end
     end else begin
        assign z = 1'b0;
     end
-endgenerate
 
 endmodule // test

tests/indent_generate_case.v

@@ -24,3 +24,34 @@ endcase
 endgenerate
 
 endmodule
+
+
+
+
+// Without generate keyword
+module indent_gen_case #(parameter P = 0)
+(input d, output reg q);
+
+
+case (P)
+0: always @(*)
+q = d;
+
+1: begin
+always @(*)
+q = d;
+end
+
+2: always @(*) begin
+q = d;
+end
+
+3: begin
+always @(*) begin
+q = d;
+end
+end
+endcase
+
+
+endmodule

tests/indent_generate_for.v

@@ -16,3 +16,26 @@ end
 endgenerate
 
 endmodule
+
+
+
+
+// Without generate keyword
+module indent_gen_for #(parameter P = 1)
+(input d, output reg q);
+
+genvar i;
+
+for (i = 0; i < P; i += 1) begin
+always @(*) begin
+q = d;
+end
+end
+
+for (i = 0; i < P; i += 1) begin
+always @(*)
+q = d;
+end
+
+
+endmodule

tests/indent_generate_if.v

@@ -24,3 +24,33 @@ end
 endgenerate
 
 endmodule
+
+
+
+// Without generate keyword
+module indent_gen_if #(parameter P = 0)
+(input d, output reg q);
+
+
+if (P == 0) begin
+always @(*)
+q = d;
+end
+
+if (P == 1) begin
+always @(*) begin
+q = d;
+end
+end
+
+if (P == 1) begin
+always @(*)
+q = d;
+end
+else begin
+always @(*)
+q = d + 1'b1;
+end
+
+
+endmodule

tests_ok/autoreset_inf_bug325.v

@@ -6,4 +6,4 @@ module aaa();
       // note missing e-n-d
       always @(*) begin
       end
-endmodule
+      endmodule

tests_ok/indent_generate.v

@@ -13,3 +13,19 @@ module test();
    endgenerate
 endmodule // test
 
+
+module test();
+   
+   reg [3:0] x;
+   
+   genvar    i;
+   
+   for(i=0; i<4; i=i+1) begin:a
+      always @(*) begin
+         x[i] = 1;
+      end
+      wire y = 0;
+   end
+   
+endmodule // test
+

tests_ok/indent_generate_bug1257.v

@@ -0,0 +1,97 @@
+// Issue #1257
+
+module t1
+  (
+   );
+   
+   genvar      pipe;
+   logic [1:0] v;
+   logic       x;
+   
+   //generate
+   for (pipe=0; pipe<2; pipe++) begin : v_bl
+      always_comb begin
+         assign v[pipe] = '0;
+      end
+      assign x = '0;  // will be incorrectly indented to column 0
+   end
+   //endgenerate
+   
+endmodule
+
+
+
+
+module indent;
+   
+   // CASE 1 indented wrong.  See end of module
+   for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
+      for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
+         if (`asdf [aa]) begin : gen_jj
+            
+            always_ff @ (negedge cc [aa][bb]) begin
+               if (dd [aa][bb])) begin
+                  for (uint_t d_idx = 0; d_idx < 16; d_idx++)
+                    ee [aa][bb].push_front (tx_dfe_out [aa][bb]  [15 - d_idx]);
+               end
+            end
+            
+            always_ff @ (posedge hs_clk) begin
+               ee_size [aa][bb] = ee [aa][bb].size();
+               if (ee_size [aa][bb] > 0)
+                 gg [aa][bb] <= ee [aa][bb].pop_front;
+            end
+            
+         end : gen_jj
+      end : gen_ii
+   end : gen_hh
+   
+   
+   
+   // this indents correctly without generate/endgenerate
+   for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
+      for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
+         if (`asdf [aa]) begin : gen_jj
+            assign a[aa][bb] = aa + bb;
+            assign b[aa][bb] = aa + bb;
+         end : gen_jj
+      end : gen_ii
+   end : gen_hh
+   
+   
+   // this works now with gen/endgen
+   generate
+      for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
+         for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
+            always @ (negedge cc)
+              a = 5;
+            always @ (negedge dd)
+              w = 2;
+         end : gen_ii
+      end : gen_hh
+   endgenerate
+   
+   
+   // CASE 1 again. No change but works - apparently since verilog-mode hit a generate statement above this line
+   for (genvar aa = 0; aa < FF; aa++) begin : gen_hh
+      for (genvar bb = 0; bb < FF; bb++) begin : gen_ii
+         if (`asdf [aa]) begin : gen_jj
+            
+            always_ff @ (negedge cc [aa][bb]) begin
+               if (dd [aa][bb])) begin
+                  for (uint_t d_idx = 0; d_idx < 16; d_idx++)
+                    ee [aa][bb].push_front (tx_dfe_out [aa][bb]  [15 - d_idx]);
+               end
+            end
+            
+            always_ff @ (posedge hs_clk) begin
+               ee_size [aa][bb] = ee [aa][bb].size();
+               if (ee_size [aa][bb] > 0)
+                 gg [aa][bb] <= ee [aa][bb].pop_front;
+            end
+            
+         end : gen_jj
+      end : gen_ii
+   end : gen_hh
+   
+endmodule : indent