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Support AUTONOHOOKUP to not AUTOWIRE hookup AUTO_TEMPLATE signals. (#1526)
* verilog-mode.el (verilog-auto-inst, verilog-auto-inst-port) (verilog-read-auto-template-middle, verilog-read-sub-decls-line): Support AUTONOHOOKUP to not AUTOWIRE hookup AUTO_TEMPLATE signals. (#1526) Reported by firefoxtc.
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+207
-18
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4 files changed

+207
-18
lines changed

tests/autoinput_nohookup.v

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module xyz (/*AUTOARG*/
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// Outputs
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signal_f, signal_c,
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// Inputs
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signal_e3, signal_b
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input [2:0] signal_b; // To u_abc of abc.v
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input signal_e3; // To u_def of def.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output signal_c; // From u_abc of abc.v
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output signal_f; // From u_def of def.v
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// End of automatics
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/*AUTOWIRE*/
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/* abc AUTO_TEMPLATE
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(
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// Outputs
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.signal_c (signal_c),
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// Inputs
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.signal_a (signal_f), // AUTONOHOOKUP
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.signal_b (signal_b[2:0]));
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*/
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abc u_abc
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(/*AUTOINST*/
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// Outputs
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.signal_c (signal_c), // Templated
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// Inputs
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.signal_a (signal_f), // Templated AUTONOHOOKUP
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.signal_b (signal_b[2:0])); // Templated
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/* def AUTO_TEMPLATE
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(// Outputs
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.signal_f (signal_f),
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// Inputs
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.signal_d (signal_c), // AUTONOHOOKUP
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.signal_e (signal_e), // AUTONOHOOKUP
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.signal_e2 (signal_e2), // AUTONOHOOKUP
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.signal_e3 ((signal_e3)),
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);
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*/
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def u_def
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(/*AUTOINST*/
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// Outputs
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.signal_f (signal_f), // Templated
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// Inputs
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.signal_d (signal_c), // Templated AUTONOHOOKUP
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.signal_e (signal_e), // Templated AUTONOHOOKUP
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.signal_e2 (signal_e2), // Templated AUTONOHOOKUP
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.signal_e3 ((signal_e3))); // Templated
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endmodule // xyz
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module abc (/*AUTOARG*/
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// Outputs
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signal_c,
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// Inputs
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signal_a, signal_b
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);
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input [1:0] signal_a;
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input [2:0] signal_b;
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output signal_c;
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endmodule // abc
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module def (/*AUTOARG*/
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// Outputs
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signal_f,
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// Inputs
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signal_d, signal_e, signal_e2, signal_e3
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);
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input [1:0] signal_d;
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input [2:0] signal_e;
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input [3:0] signal_e2;
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input [3:0] signal_e3;
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output signal_f;
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endmodule // def

tests_ok/autoinput_concat_ignore.v

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,22 @@
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module xyz (/*AUTOARG*/
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// Outputs
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signal_f, signal_c,
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// Inputs
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signal_b
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signal_e3, signal_e, signal_b
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input [2:0] signal_b; // To u_abc of abc.v
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input signal_e; // To u_def of def.v
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input signal_e3; // To u_def of def.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output signal_c; // From u_abc of abc.v
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output signal_f; // From u_def of def.v
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire signal_c; // From u_abc of abc.v
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wire signal_f; // From u_def of def.v
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// End of automatics
2020

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/* abc AUTO_TEMPLATE
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(

tests_ok/autoinput_nohookup.v

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module xyz (/*AUTOARG*/
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// Outputs
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signal_f, signal_c,
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// Inputs
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signal_e3, signal_b
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);
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input [2:0] signal_b; // To u_abc of abc.v
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input signal_e3; // To u_def of def.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output signal_c; // From u_abc of abc.v
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output signal_f; // From u_def of def.v
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// End of automatics
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/*AUTOWIRE*/
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/* abc AUTO_TEMPLATE
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(
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// Outputs
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.signal_c (signal_c),
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// Inputs
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.signal_a (signal_f), // AUTONOHOOKUP
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.signal_b (signal_b[2:0]));
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*/
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abc u_abc
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(/*AUTOINST*/
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// Outputs
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.signal_c (signal_c), // Templated
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// Inputs
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.signal_a (signal_f), // Templated AUTONOHOOKUP
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.signal_b (signal_b[2:0])); // Templated
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/* def AUTO_TEMPLATE
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(// Outputs
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.signal_f (signal_f),
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// Inputs
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.signal_d (signal_c), // AUTONOHOOKUP
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.signal_e (signal_e), // AUTONOHOOKUP
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.signal_e2 (signal_e2), // AUTONOHOOKUP
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.signal_e3 ((signal_e3)),
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);
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*/
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def u_def
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(/*AUTOINST*/
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// Outputs
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.signal_f (signal_f), // Templated
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// Inputs
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.signal_d (signal_c), // Templated AUTONOHOOKUP
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.signal_e (signal_e), // Templated AUTONOHOOKUP
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.signal_e2 (signal_e2), // Templated AUTONOHOOKUP
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.signal_e3 ((signal_e3))); // Templated
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endmodule // xyz
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module abc (/*AUTOARG*/
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// Outputs
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signal_c,
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// Inputs
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signal_a, signal_b
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);
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input [1:0] signal_a;
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input [2:0] signal_b;
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output signal_c;
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endmodule // abc
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module def (/*AUTOARG*/
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// Outputs
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signal_f,
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// Inputs
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signal_d, signal_e, signal_e2, signal_e3
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);
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input [1:0] signal_d;
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input [2:0] signal_e;
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input [3:0] signal_e2;
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input [3:0] signal_e3;
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output signal_f;
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endmodule // def

verilog-mode.el

Lines changed: 24 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -829,7 +829,7 @@ The name of the function or case will be set between the braces."
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(defcustom verilog-auto-ignore-concat nil
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"Non-nil means ignore signals in {...} concatenations for AUTOWIRE etc.
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This will exclude signals referenced as pin connections in {...}
832-
or (...) from AUTOWIRE, AUTOOUTPUT and friends."
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or (...) from AUTOWIRE, AUTOOUTPUT and friends. See also AUTONOHOOKUP."
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:group 'verilog-mode-actions
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:type 'boolean)
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(put 'verilog-auto-ignore-concat 'safe-local-variable #'verilog-booleanp)
@@ -9106,9 +9106,7 @@ Inserts the list of signals found, using submodi to look up each port."
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;; We intentionally ignore (non-escaped) signals with .s in them
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;; this prevents AUTOWIRE etc from noticing hierarchical sigs.
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(when port
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(cond ((and verilog-auto-ignore-concat
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(looking-at "[({]"))
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nil) ; {...} or (...) historically ignored with auto-ignore-concat
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(cond ((looking-at "[^\n]*AUTONOHOOKUP"))
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((looking-at "\\([a-zA-Z_][a-zA-Z_0-9]*\\)\\s-*)")
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(verilog-read-sub-decls-sig
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submoddecls par-values comment port
@@ -9555,7 +9553,10 @@ Returns REGEXP and list of ( (signal_name connection_name)... )."
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(cons (list
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(match-string-no-properties 1)
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(match-string-no-properties 2)
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templateno lineno)
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templateno lineno
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(save-excursion
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(goto-char (match-end 0))
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(looking-at "[^\n]*AUTONOHOOKUP")))
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tpl-sig-list))
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(goto-char (match-end 0)))
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;; Regexp form??
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(match-string 1))
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"$")
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rep
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templateno lineno)
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templateno lineno
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(save-excursion
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(goto-char (match-end 0))
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(looking-at "[^\n]*AUTONOHOOKUP")))
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tpl-wild-list)))
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((looking-at "[ \t\f]+")
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(goto-char (match-end 0)))
@@ -11689,15 +11693,14 @@ If PAR-VALUES replace final strings with these parameter values."
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;; verilog-insert requires the complete comment in one call - including the newline
1169011694
(cond ((equal verilog-auto-inst-template-numbers 'lhs)
1169111695
(verilog-insert " // Templated"
11692-
" LHS: " (nth 0 tpl-ass)
11693-
"\n"))
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" LHS: " (nth 0 tpl-ass)))
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(verilog-auto-inst-template-numbers
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(verilog-insert " // Templated"
1169611699
" T" (int-to-string (nth 2 tpl-ass))
11697-
" L" (int-to-string (nth 3 tpl-ass))
11698-
"\n"))
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" L" (int-to-string (nth 3 tpl-ass))))
1169911701
(t
11700-
(verilog-insert " // Templated\n"))))
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(verilog-insert " // Templated")))
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(verilog-insert (if (nth 4 tpl-ass) " AUTONOHOOKUP\n" "\n")))
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(for-star
1170211705
(indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
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verilog-auto-inst-column))
@@ -12087,6 +12090,16 @@ Lisp Templates:
1208712090
After the evaluation is completed, @ substitution and [] substitution
1208812091
occur.
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Ignoring Hookup:
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AUTOWIRE and related AUTOs will read the signals created by a template.
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To specify that a signal should not be parsed to participate in this
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hookup, add a AUTONOHOOKUP comment to the template. For example:
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12100+
.pci_req_l (pci_req_not_to_wire), //AUTONOHOOKUP
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1209012103
For more information see the \\[verilog-faq] and forums at URL
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`https://www.veripool.org'."
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(save-excursion

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