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urishurish
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feat(spi): implement SPI peripheral
not yet tested
1 parent 159f6fa commit 3c7c5c7

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2 files changed

+246
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‎src/peripherals/spi.ts‎

Lines changed: 237 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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import { RP2040 } from '../rp2040';
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import { FIFO } from '../utils/fifo';
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import { BasePeripheral, Peripheral } from './peripheral';
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const SSPCR0 = 0x000; // Control register 0, SSPCR0 on page 3-4
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const SSPCR1 = 0x004; // Control register 1, SSPCR1 on page 3-5
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const SSPDR = 0x008; // Data register, SSPDR on page 3-6
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const SSPSR = 0x00c; // Status register, SSPSR on page 3-7
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const SSPCPSR = 0x010; // Clock prescale register, SSPCPSR on page 3-8
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const SSPIMSC = 0x014; // Interrupt mask set or clear register, SSPIMSC on page 3-9
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const SSPRIS = 0x018; // Raw interrupt status register, SSPRIS on page 3-10
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const SSPMIS = 0x01c; // Masked interrupt status register, SSPMIS on page 3-11
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const SSPICR = 0x020; // Interrupt clear register, SSPICR on page 3-11
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const SSPDMACR = 0x024; // DMA control register, SSPDMACR on page 3-12
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const SSPPERIPHID0 = 0xfe0; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
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const SSPPERIPHID1 = 0xfe4; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
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const SSPPERIPHID2 = 0xfe8; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
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const SSPPERIPHID3 = 0xfec; // Peripheral identification registers, SSPPeriphID0-3 on page 3-13
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const SSPPCELLID0 = 0xff0; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
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const SSPPCELLID1 = 0xff4; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
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const SSPPCELLID2 = 0xff8; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
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const SSPPCELLID3 = 0xffc; // PrimeCell identification registers, SSPPCellID0-3 on page 3-16
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// SSPCR0 bits:
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const SCR_MASK = 0xff;
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const SCR_SHIFT = 8;
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const SPH = 1 << 7;
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const SPO = 1 << 6;
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const FRF_MASK = 0x3;
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const FRF_SHIFT = 4;
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const DSS_MASK = 0xf;
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const DSS_SHIFT = 0;
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// SSPCR1 bits:
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const SOD = 1 << 3;
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const MS = 1 << 2;
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const SSE = 1 << 1;
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const LBM = 1 << 0;
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// SSPSR bits:
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const BSY = 1 << 4;
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const RFF = 1 << 3;
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const RNE = 1 << 2;
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const TNF = 1 << 1;
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const TFE = 1 << 0;
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// SSPCPSR bits:
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const CPSDVSR_MASK = 0xfe;
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const CPSDVSR_SHIFT = 0;
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// SSPDMACR bits:
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const TXDMAE = 1 << 1;
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const RXDMAE = 1 << 0;
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// Interrupts:
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const SSPTXINTR = 1 << 3;
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const SSPRXINTR = 1 << 2;
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const SSPRTINTR = 1 << 1;
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const SSPRORINTR = 1 << 0;
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export class RPSPI extends BasePeripheral implements Peripheral {
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readonly rxFIFO = new FIFO(8);
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readonly txFIFO = new FIFO(8);
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// User provided callbacks
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onTransmit: (value: number) => void = () => this.completeTransmit(0);
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private busy = false;
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private control0 = 0;
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private control1 = 0;
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private dmaControl = 0;
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private clockDivisor = 0;
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private intRaw = 0;
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private intEnable = 0;
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get intStatus() {
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return this.intRaw & this.intEnable;
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}
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get enabled() {
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return !!(this.control1 & SSE);
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}
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/** Data size in bits: 4 to 16 bits */
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get dataBits() {
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return ((this.control0 >> DSS_SHIFT) & DSS_MASK) + 1;
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}
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get masterMode() {
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return !(this.control0 & MS);
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}
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get spiMode() {
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const cpol = this.control0 & SPO;
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const cpha = this.control0 & SPH;
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return cpol ? (cpha ? 2 : 3) : cpha ? 1 : 0;
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}
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get clockFrequency() {
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if (!this.clockDivisor) {
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return 0;
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}
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const scr = (this.control0 >> SCR_SHIFT) & SCR_MASK;
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return this.rp2040.clkPeri / (this.clockDivisor * (1 + scr));
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}
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constructor(rp2040: RP2040, name: string, readonly irq: number) {
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super(rp2040, name);
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}
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private doTX() {
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if (!this.busy && !this.txFIFO.empty) {
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const value = this.txFIFO.pull();
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this.onTransmit(value);
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this.busy = true;
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this.fifosUpdated();
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}
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}
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completeTransmit(rxValue: number) {
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this.busy = false;
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if (!this.rxFIFO.full) {
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this.rxFIFO.push(rxValue);
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} else {
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this.intRaw |= SSPRORINTR;
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}
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this.fifosUpdated();
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this.doTX();
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}
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checkInterrupts() {
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this.rp2040.setInterrupt(this.irq, !!this.intStatus);
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}
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private fifosUpdated() {
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const prevStatus = this.intStatus;
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if (this.txFIFO.itemCount <= this.txFIFO.size / 2) {
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this.intRaw |= SSPTXINTR;
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} else {
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this.intRaw &= ~SSPTXINTR;
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}
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if (this.rxFIFO.itemCount >= this.rxFIFO.size / 2) {
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this.intRaw |= SSPRXINTR;
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} else {
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this.intRaw &= ~SSPRXINTR;
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}
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if (this.intStatus !== prevStatus) {
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this.checkInterrupts();
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}
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}
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readUint32(offset: number) {
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switch (offset) {
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case SSPCR0:
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return this.control0;
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case SSPCR1:
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return this.control1;
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case SSPDR:
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if (!this.rxFIFO.empty) {
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const value = this.rxFIFO.pull();
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this.fifosUpdated();
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return value;
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}
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return 0;
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case SSPSR:
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return (
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(this.busy || !this.txFIFO.empty ? BSY : 0) |
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(this.rxFIFO.full ? RFF : 0) |
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(!this.rxFIFO.empty ? RNE : 0) |
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(!this.txFIFO.full ? TNF : 0) |
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(this.txFIFO.empty ? TFE : 0)
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);
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case SSPCPSR:
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return this.clockDivisor;
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case SSPIMSC:
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return this.intEnable;
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case SSPRIS:
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return this.intRaw;
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case SSPMIS:
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return this.intStatus;
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case SSPDMACR:
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return this.dmaControl;
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case SSPPERIPHID0:
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return 0x22;
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case SSPPERIPHID1:
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return 0x10;
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case SSPPERIPHID2:
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return 0x34;
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case SSPPERIPHID3:
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return 0x00;
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case SSPPCELLID0:
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return 0x0d;
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case SSPPCELLID1:
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return 0xf0;
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case SSPPCELLID2:
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return 0x05;
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case SSPPCELLID3:
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return 0xb1;
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}
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return super.readUint32(offset);
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}
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writeUint32(offset: number, value: number) {
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switch (offset) {
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case SSPCR0:
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this.control0 = value;
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return;
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case SSPCR1:
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this.control1 = value;
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return;
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case SSPDR:
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if (!this.txFIFO.full) {
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this.txFIFO.push(value);
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this.doTX();
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this.fifosUpdated();
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}
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return;
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case SSPCPSR:
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this.clockDivisor = value & CPSDVSR_MASK;
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return;
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case SSPIMSC:
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this.intEnable = value;
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this.checkInterrupts();
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return;
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case SSPDMACR:
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this.dmaControl = value;
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return;
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case SSPICR:
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this.intRaw &= ~(value & (SSPRTINTR | SSPRORINTR));
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this.checkInterrupts();
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return;
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default:
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super.writeUint32(offset, value);
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}
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}
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}

‎src/rp2040.ts‎

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ import { RPPIO } from './peripherals/pio';
1212
import { RPPPB } from './peripherals/ppb';
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import { RPReset } from './peripherals/reset';
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import { RP2040RTC } from './peripherals/rtc';
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import { RPSPI } from './peripherals/spi';
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import { RPSSI } from './peripherals/ssi';
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import { RP2040SysCfg } from './peripherals/syscfg';
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import { RPTimer } from './peripherals/timer';
@@ -79,6 +80,7 @@ const LOG_NAME = 'RP2040';
7980

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const KB = 1024;
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const MB = 1024 * KB;
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const MHz = 1_000_000;
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8385
export class RP2040 {
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readonly bootrom = new Uint32Array(4 * KB);
@@ -93,11 +95,16 @@ export class RP2040 {
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bankedSP: number = 0;
9496
cycles: number = 0;
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/* Clocks */
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clkSys = 125 * MHz;
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clkPeri = 125 * MHz;
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96102
readonly ppb = new RPPPB(this, 'PPB');
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readonly sio = new RPSIO(this);
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readonly uart = [new RPUART(this, 'UART0', IRQ.UART0), new RPUART(this, 'UART1', IRQ.UART1)];
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readonly i2c = [new RPI2C(this, 'I2C0', IRQ.I2C0), new RPI2C(this, 'I2C1', IRQ.I2C1)];
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readonly spi = [new RPSPI(this, 'SPI0', IRQ.SPI0), new RPSPI(this, 'SPI1', IRQ.SPI1)];
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readonly adc = new RPADC(this, 'ADC');
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103110
readonly gpio = [
@@ -199,8 +206,8 @@ export class RP2040 {
199206
0x40030: new UnimplementedPeripheral(this, 'BUSCTRL_BASE'),
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0x40034: this.uart[0],
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0x40038: this.uart[1],
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0x4003c: new UnimplementedPeripheral(this, 'SPI0_BASE'),
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0x40040: new UnimplementedPeripheral(this, 'SPI1_BASE'),
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0x4003c: this.spi[0],
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0x40040: this.spi[1],
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0x40044: this.i2c[0],
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0x40048: this.i2c[1],
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0x4004c: this.adc,

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