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fix(rp2040): Fix CMP reg T1 carry flag (#31)
1 parent 7f3ee53 commit 813cdca

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2 files changed

+16
-4
lines changed

2 files changed

+16
-4
lines changed

src/instructions.spec.ts

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -469,6 +469,18 @@ describe('Cortex-M0+ Instruction Set', () => {
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expect(registers.V).toEqual(false);
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});
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it('should execute an `cmp r2, r0` instruction and not set any flags when r0=0xb71b0000 and r2=0x00b71b00', async () => {
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await cpu.setPC(0x20000000);
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await cpu.writeUint16(0x20000000, opcodeCMPregT1(r2, r0));
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await cpu.setRegisters({ r0: 0xb71b0000, r2: 0x00b71b00 });
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await cpu.singleStep();
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const registers = await cpu.readRegisters();
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expect(registers.N).toEqual(false);
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expect(registers.Z).toEqual(false);
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expect(registers.C).toEqual(false);
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expect(registers.V).toEqual(false);
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});
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it('should correctly set carry flag when executing `cmp r11, r3` instruction', async () => {
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await cpu.setPC(0x20000000);
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await cpu.writeUint16(0x20000000, opcodeCMPregT2(r11, r3));

src/rp2040.ts

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1028,10 +1028,10 @@ export class RP2040 {
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else if (opcode >> 6 === 0b0100001010) {
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const Rm = (opcode >> 3) & 0x7;
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const Rn = opcode & 0x7;
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const leftValue = this.registers[Rn] | 0;
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const rightValue = this.registers[Rm] | 0;
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const result = (leftValue - rightValue) | 0;
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this.N = leftValue < rightValue;
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const leftValue = this.registers[Rn];
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const rightValue = this.registers[Rm];
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const result = ((leftValue | 0) - (rightValue | 0)) | 0;
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this.N = result < 0;
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this.Z = leftValue === rightValue;
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this.C = leftValue >= rightValue;
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this.V =

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