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miyazakhdanielinux
miyazakh
authored and
danielinux
committed
add raspi3b uart
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‎config/examples/raspi3.config

+1
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ SPMATH?=1
88
IMAGE_HEADER_SIZE?=1024
99
PKA?=1
1010
WOLFTPM?=0
11+
DEBUG_UART?=0
1112
WOLFBOOT_SECTOR_SIZE=0x400
1213
WOLFBOOT_NO_PARTITIONS=1
1314
WOLFBOOT_LOAD_ADDRESS?=0x3080000

‎docs/Targets.md

+58-2
Original file line numberDiff line numberDiff line change
@@ -1089,7 +1089,7 @@ git clone https://github.com/raspberrypi/linux linux-rpi -b rpi-4.19.y --depth=1
10891089
export wolfboot_dir=`pwd`
10901090
cd linux-rpi
10911091
patch -p1 < $wolfboot_dir/tools/wolfboot-rpi-devicetree.diff
1092-
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- bcmrpi3_defconfig
1092+
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- bcm2711_defconfig
10931093
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu-
10941094
```
10951095

@@ -1126,10 +1126,66 @@ dd if=bcm2710-rpi-3-b.dtb of=wolfboot_linux_raspi.bin bs=1 seek=128K conv=notrun
11261126

11271127
* Test boot using qemu
11281128

1129+
Download [root file system image(2020-02-13-raspbian-buster-lite.zip)](https://ftp.jaist.ac.jp/pub/raspberrypi/raspbian_lite/images/raspbian_lite-2020-02-14/2020-02-13-raspbian-buster-lite.zip)
11291130
```
1130-
qemu-system-aarch64 -M raspi3b -m 1024 -serial stdio -kernel wolfboot_linux_raspi.bin -cpu cortex-a53
1131+
qemu-system-aarch64 -M raspi3b -m 1024 -serial stdio -kernel wolfboot_linux_raspi.bin -cpu cortex-a53 -drive file=../wolfboot/2020-02-13-raspbian-buster-lite.img,if=sd,format=raw
1132+
```
1133+
1134+
### Testing on [Raspberry PI 3 B Plus](https://www.raspberrypi.com/products/raspberry-pi-3-model-b-plus/)
1135+
1136+
* Copy dtb file for Raspberry PI 3 B Plus to the wolfboot directory
1137+
1138+
```
1139+
cp /path/to/raspberry-pi-linux/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dtb $wolfboot_dir
1140+
cd $wolfboot_dir
1141+
```
1142+
1143+
* Compose the image
1144+
```
1145+
dd if=bcm2710-rpi-3-b-plus.dtb of=wolfboot_linux_raspi.bin bs=1 seek=128K conv=notrunc
1146+
```
1147+
1148+
* Copy the kernel image to boot partition of boot media. e.g. SD card
1149+
1150+
Raspberry Pi loads `kernel8.img` when it is in `AArch64` mode. Therefore, the kernel image is copied to boot partition as `kernel8.img` file name.
1151+
```
1152+
cp wolfboot_linux_raspi.bin /media/foo/boot/kernel8.img
11311153
```
11321154

1155+
* Troubleshooting
1156+
1157+
o Turn on UART for debugging to know what boot-process is going on. Chaning DEBUG_UART property in .config to 1.
1158+
```
1159+
DEBUG_UART?=1
1160+
```
1161+
UART properties set as 115200 bps, 8bit data transmission, 1 stop bit and no parity.
1162+
1163+
You would see the following message when wolfboot starts.
1164+
```
1165+
My board version is: 0xA020D3
1166+
Trying partition 0 at 0x140000
1167+
Boot partition: 0x140000 (size 14901760, version 0x1)
1168+
....
1169+
````
1170+
Note: Now, integrity-check takes 2 - 3 minutes to complete before running Linux kernel.
1171+
1172+
o Kernel panic after wolfboot message
1173+
Mount position of root file system could be wrong. Checking your boot media by `lsblk` command.
1174+
```
1175+
$ lsblk
1176+
NAME MAJ:MIN RM SIZE RO TYPE MOUNTPOINT
1177+
mmcblk0 179:0 0 29.7G 0 disk
1178+
├─mmcblk0p1 179:1 0 63M 0 part
1179+
├─mmcblk0p2 179:2 0 1K 0 part
1180+
├─mmcblk0p5 179:5 0 32M 0 part
1181+
├─mmcblk0p6 179:6 0 66M 0 part /boot
1182+
└─mmcblk0p7 179:7 0 29.6G 0 part /
1183+
```
1184+
1185+
It need to modify dtb file accordingly. Go to /path/to/raspberry-pi-linux/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts. Change `root=/dev/mmcblk0p7` of the following line in the file to your root file system device.
1186+
```
1187+
bootargs = "coherent_pool=1M 8250.nr_uarts=1 console=ttyAMA0,115200 console=tty1 root=/dev/mmcblk0p7 rootfstype=ext4 elevator=deadline fsck.repair=yes rootwait splash plymouth.ignore-serial-consoles";
1188+
```
11331189
11341190
### Testing with kernel encryption
11351191

‎hal/raspi3.c

+255-3
Original file line numberDiff line numberDiff line change
@@ -18,23 +18,209 @@
1818
* along with this program; if not, write to the Free Software
1919
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
2020
*/
21-
21+
#include <stddef.h>
2222
#include <stdint.h>
2323
#include <string.h>
2424
#include <target.h>
2525
#include "image.h"
26+
#include "printf.h"
2627
#ifndef ARCH_AARCH64
2728
# error "wolfBoot raspi3 HAL: wrong architecture selected. Please compile with ARCH=AARCH64."
2829
#endif
2930

3031
#define TEST_ENCRYPT
3132

33+
#if defined(DEBUG_UART)
34+
#define PRINTF_ENABLED
35+
#endif
36+
3237

3338
#define CORTEXA53_0_CPU_CLK_FREQ_HZ 1099989014
3439
#define CORTEXA53_0_TIMESTAMP_CLK_FREQ 99998999
3540

41+
#define MMIO_BASE 0x3F000000
42+
43+
#define GPIO_BASE MMIO_BASE + 0x200000
44+
45+
#define GPFSEL1 ((volatile unsigned int*)(GPIO_BASE+0x04))
46+
#define GPPUD ((volatile unsigned int*)(GPIO_BASE+0x94))
47+
#define GPPUDCLK0 ((volatile unsigned int*)(GPIO_BASE+0x98))
48+
49+
/* PL011 UART registers */
50+
#define UART0_BASE GPIO_BASE + 0x1000
51+
#define UART0_DR ((volatile unsigned int*)(UART0_BASE+0x00))
52+
#define UART0_FR ((volatile unsigned int*)(UART0_BASE+0x18))
53+
#define UART0_IBRD ((volatile unsigned int*)(UART0_BASE+0x24))
54+
#define UART0_FBRD ((volatile unsigned int*)(UART0_BASE+0x28))
55+
#define UART0_LCRH ((volatile unsigned int*)(UART0_BASE+0x2C))
56+
#define UART0_CR ((volatile unsigned int*)(UART0_BASE+0x30))
57+
#define UART0_IMSC ((volatile unsigned int*)(UART0_BASE+0x38))
58+
#define UART0_ICR ((volatile unsigned int*)(UART0_BASE+0x44))
59+
60+
/* mail box message buffer */
61+
volatile unsigned int __attribute__((aligned(16))) mbox[36];
62+
63+
#define VIDEOCORE_MBOX (MMIO_BASE+0x0000B880)
64+
#define MBOX_READ ((volatile unsigned int*)(VIDEOCORE_MBOX+0x0))
65+
#define MBOX_POLL ((volatile unsigned int*)(VIDEOCORE_MBOX+0x10))
66+
#define MBOX_SENDER ((volatile unsigned int*)(VIDEOCORE_MBOX+0x14))
67+
#define MBOX_STATUS ((volatile unsigned int*)(VIDEOCORE_MBOX+0x18))
68+
#define MBOX_CONFIG ((volatile unsigned int*)(VIDEOCORE_MBOX+0x1C))
69+
#define MBOX_WRITE ((volatile unsigned int*)(VIDEOCORE_MBOX+0x20))
70+
#define MBOX_RESPONSE 0x80000000
71+
#define MBOX_FULL 0x80000000
72+
#define MBOX_EMPTY 0x40000000
73+
74+
#define MBOX_REQUEST 0
75+
76+
/* channels */
77+
#define MBOX_CH_POWER 0
78+
#define MBOX_CH_FB 1
79+
#define MBOX_CH_VUART 2
80+
#define MBOX_CH_VCHIQ 3
81+
#define MBOX_CH_LEDS 4
82+
#define MBOX_CH_BTNS 5
83+
#define MBOX_CH_TOUCH 6
84+
#define MBOX_CH_COUNT 7
85+
#define MBOX_CH_PROP 8
86+
87+
/* tags */
88+
#define MBOX_TAG_GETBRDVERSION 0x10002
89+
#define MBOX_TAG_GETSERIAL 0x10004
90+
#define MBOX_TAG_GET_CLOCK_RATE 0x30002
91+
#define MBOX_TAG_SETCLKRATE 0x38002
92+
#define MBOX_TAG_LAST 0
93+
3694
/* Fixed addresses */
3795
extern void *kernel_addr, *update_addr, *dts_addr;
96+
/* Loop <delay> times */
97+
static inline void delay(int32_t count)
98+
{
99+
register unsigned int c;
100+
c = count;
101+
while (c--) {
102+
asm volatile("nop");
103+
}
104+
}
105+
/**
106+
* write message to mailbox
107+
*/
108+
static void mailbox_write(uint8_t chan)
109+
{
110+
uint32_t ch = (((uint32_t)((unsigned long)&mbox) & ~0xf)
111+
| (chan & 0xf));
112+
113+
/* wait until mail box becomes ready to write */
114+
while ((*MBOX_STATUS & MBOX_FULL) != 0) { }
115+
116+
/* write the address of the message to mail-box channel */
117+
*MBOX_WRITE = ch;
118+
}
119+
/**
120+
* read message from mailbox
121+
*/
122+
static int mailbox_read(uint8_t chan)
123+
{
124+
uint32_t ch = (((uint32_t)((unsigned long)&mbox) & ~0xf)
125+
| (chan & 0xf));
126+
/* now wait for the response */
127+
while(1) {
128+
while ((*MBOX_STATUS & MBOX_EMPTY) != 0) { }
129+
if(ch == *MBOX_READ)
130+
/* is it a valid successful response */
131+
return mbox[1] == MBOX_RESPONSE;
132+
}
133+
return 0;
134+
}
135+
136+
/* UART functions for Raspberry Pi 3 UART */
137+
void uart_tx(char c)
138+
{
139+
/* wait until uart channel is ready to send */
140+
do{
141+
asm volatile("nop");
142+
} while(*UART0_FR & 0x20);
143+
*UART0_DR = c;
144+
}
145+
146+
char uart_read(void)
147+
{
148+
char c;
149+
/* wait until data is comming */
150+
do{
151+
asm volatile("nop");
152+
} while(*UART0_FR & 0x10);
153+
/* read it and return */
154+
c = (char)(*UART0_DR);
155+
/* convert carrige return to newline */
156+
if (c == '\r')
157+
c = '\n';
158+
159+
return c;
160+
}
161+
162+
/**
163+
* Send string to UART
164+
*/
165+
void uart_write(const char* buf, uint32_t sz) {
166+
uint32_t len = sz;
167+
168+
while (len > 0 && *buf) {
169+
/* convert newline to carrige return + newline */
170+
if (*buf == '\n')
171+
uart_tx('\r');
172+
173+
uart_tx(*buf++);
174+
len--;
175+
}
176+
}
177+
178+
void uart_init()
179+
{
180+
register unsigned int c;
181+
182+
/* initialize UART. turn off UART 0*/
183+
*UART0_CR = 0;
184+
185+
/* set up clock for consistent divisor values */
186+
mbox[0] = 9 * 4;
187+
mbox[1] = MBOX_REQUEST;
188+
/* tag for setting clock rate */
189+
mbox[2] = MBOX_TAG_SETCLKRATE;
190+
mbox[3] = 12;
191+
mbox[4] = 8;
192+
/* specify UART clock channel */
193+
mbox[5] = 2;
194+
/* UART clock rate in hz(4Mhz)*/
195+
mbox[6] = 4000000;
196+
/* not use turbo */
197+
mbox[7] = 0;
198+
mbox[8] = MBOX_TAG_LAST;
199+
200+
mailbox_write(MBOX_CH_PROP);
201+
mailbox_read(MBOX_CH_PROP);
202+
203+
/* disable pull up/down for all GPIO pins */
204+
*GPPUD = 0;
205+
delay(150);
206+
/* Disable pull up/down for pin 14 and 15 */
207+
*GPPUDCLK0 = (1<<14)|(1<<15);
208+
delay(150);
209+
/* flush GPIO setting to make it take effect */
210+
*GPPUDCLK0 = 0;
211+
212+
/* clear pending interrupts */
213+
*UART0_ICR = 0x7FF;
214+
/* select 115200 baud rate */
215+
/* divider = 4000000 / (16 * 115200) = 2.17 = ~2 */
216+
*UART0_IBRD = 2;
217+
/* Fractional part register = (.17013 * 64) + 0.5 = 11.38 = ~11 */
218+
*UART0_FBRD = 0xB;
219+
/* Enable fifo, 8bit data transmission ( 1stop bit, no parity) */
220+
*UART0_LCRH = (1 << 4) | (1 << 5) | (1 << 6);
221+
/* enable UART0 transfer & receive*/
222+
*UART0_CR = (1 << 0) | (1 << 8) | (1 << 9);
223+
}
38224

39225
void* hal_get_primary_address(void)
40226
{
@@ -91,22 +277,88 @@ void qspi_init(uint32_t cpu_clock, uint32_t flash_freq)
91277
{
92278
}
93279

94-
95280
void zynq_init(uint32_t cpu_clock)
96281
{
97282
}
98283

284+
#if defined(DISPLAY_CLOCKS)
285+
static uint32_t getclocks(uint8_t cid)
286+
{
287+
/* Retrive clock rate */
288+
/* length of the message */
289+
mbox[0] = 8 * 4;
290+
mbox[1] = MBOX_REQUEST;
291+
/* tag for get board version */
292+
mbox[2] = MBOX_TAG_GET_CLOCK_RATE;
293+
/* buffer size */
294+
mbox[3] = 8;
295+
mbox[4] = 8;
296+
/* clock id CORE*/
297+
mbox[5] = cid;
298+
/* clock frequency */
299+
mbox[6] = 0;
300+
mbox[7] = MBOX_TAG_LAST;
301+
mailbox_write(MBOX_CH_PROP);
99302

303+
if (mailbox_read(MBOX_CH_PROP)) {
304+
return mbox[6];
305+
}
306+
else {
307+
return 0;
308+
}
309+
}
310+
#endif /* DISPLAY clocks */
100311

101312
/* public HAL functions */
102313
void hal_init(void)
103314
{
104315
#if defined(TEST_ENCRYPT) && defined (EXT_ENCRYPTED)
105316
char enc_key[] = "0123456789abcdef0123456789abcdef"
106-
"0123456789abcdef";
317+
"0123456789abcdef";
107318
wolfBoot_set_encrypt_key((uint8_t *)enc_key,(uint8_t *)(enc_key + 32));
108319
#endif
109320

321+
uart_init();
322+
323+
/* length of the message */
324+
mbox[0] = 7 * 4;
325+
mbox[1] = MBOX_REQUEST;
326+
/* tag for get board version */
327+
mbox[2] = MBOX_TAG_GETBRDVERSION;
328+
/* buffer size */
329+
mbox[3] = 4;
330+
mbox[4] = 0;
331+
mbox[5] = 0;
332+
mbox[6] = MBOX_TAG_LAST;
333+
334+
/* send the message to the GPU */
335+
mailbox_write(MBOX_CH_PROP);
336+
337+
if (mailbox_read(MBOX_CH_PROP)) {
338+
wolfBoot_printf("My board version is: 0x%08x", mbox[5]);
339+
wolfBoot_printf("\n");
340+
} else {
341+
wolfBoot_printf("Unable to query board version!\n");
342+
}
343+
344+
#if defined(DISPLAY_CLOCKS) && defined(PRINTF_ENABLED)
345+
/* Get clocks */
346+
wolfBoot_printf("\n EMMC clock : %d Hz", getclocks(1));
347+
wolfBoot_printf("\n UART clock : %d Hz", getclocks(2));
348+
wolfBoot_printf("\n ARM clock : %d Hz", getclocks(3));
349+
wolfBoot_printf("\n CORE clock : %d Hz", getclocks(4));
350+
wolfBoot_printf("\n V3D clock : %d Hz", getclocks(5));
351+
wolfBoot_printf("\n H264 clock : %d Hz", getclocks(6));
352+
wolfBoot_printf("\n ISP clock : %d Hz", getclocks(7));
353+
wolfBoot_printf("\n SDRAM clock : %d Hz", getclocks(8));
354+
wolfBoot_printf("\n PIXEL clock : %d Hz", getclocks(9));
355+
wolfBoot_printf("\n PWM clock : %d Hz", getclocks(10));
356+
wolfBoot_printf("\n HEVC clock : %d Hz", getclocks(11));
357+
wolfBoot_printf("\n EMMC2 clock : %d Hz", getclocks(12));
358+
wolfBoot_printf("\n M2MC clock : %d Hz", getclocks(13));
359+
wolfBoot_printf("\n PIXEL_BVB clock : %d Hz\n", getclocks(14));
360+
#endif
361+
110362
}
111363

112364
void hal_prepare_boot(void)

‎hal/raspi3.ld

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
MEMORY
22
{
3-
DDR_MEM(rwx): ORIGIN = 0x00080000, LENGTH = 0x80000000
3+
DDR_MEM(rwx): ORIGIN = 0x00080000, LENGTH = 0x3c000000
44
}
55
ENTRY(_vector_table);
66

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