[STM32H747]SDMMC2 Clock Initialization Failure on M4 Core (PLL2R Frequency Mismatch)

[WHMJJ]

I am currently working on enabling the SDMMC2 peripheral on the Cortex-M4 core of an STM32H747I-DISCO development board running Zephyr RTOS. My project is based on the standard rpmsg_service sample, utilizing the M7/M4 dual-core architecture.

During the SDMMC2 driver initialization, the system consistently reports clock errors. The root cause appears to be a mismatch between the actual PLL2 output frequency configured by the M7 core and the frequency expected by the M4 core's Device Tree Source (DTS) overlay.

Error Details and Diagnostic Findings
The system fails to initialize the clocks, reporting: [00:00:02.001,000] stm32_sdmmc: Failed to enable SDMMC domain clock and [00:00:02.001,000] stm32_sdmmc: failed to init clocks.

Crucially, direct measurement within the application using HAL functions shows that the actual frequency of PLL2R is 64 MHz (Output: PLL2_R = 64Mhz).

However, my M4 core's DTS overlay for the PLL2 node specifies parameters (div-m=5, mul-n=96, div-r=10, with HSE=25 MHz) which mathematically calculate to 48 MHz. This conflict between the expected 48 MHz (DTS) and the measured 64 MHz (HAL) is preventing successful initialization.

Environment
Platform: stm32h757i_eval
Sample Used: samples/subsys/ipc/rpmsg_service (as the base to build the sdmmc2/FDCAN)
Zephyr Version: 0.17.2

Key Questions for SDMMC Clock Configuration
My main objective is to ensure that the M4 core’s SDMMC driver correctly reads and uses the actual SDMMC domain clock.

1. Ensuring Correct Clock Frequency on M4 SDMMC Driver
   To resolve the 64 MHz vs. 48 MHz mismatch, I need the exact PLL2 parameters (div-m, mul-n, div-r) that produce the measured 64 MHz.
   This will allow the M4 core’s DTS to align with the clock settings configured by the M7 core.
2. Recommended Dual-Core Clock Configuration Methodology
   What is the proper approach for peripheral and PLL configuration in a Zephyr M7/M4 dual-core setup?
   Should the M7 core (Host) exclusively configure and enable all PLLs?

m7/m4 overlay detail as below:
https://github.com/WHMJJ/ZEPHYR-STM32H747-DISCO-SDMMC2-M4/tree/main/rpmsg_service_Joey_ver2_addsdmmc2

stm32h747i_disco_stm32h747xx_m7.overlay
/*
 * Copyright (c) 2024 Celina Sophie Kalus <[email protected]>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/ {
	chosen {
		zephyr,ipc_shm = &sram4;
		zephyr,ipc = &mailbox;
	};
};

&mailbox {
	status = "okay";
};

// &usart1 {
// 	status = "okay";
// };

&uart8 {
	status = "okay"; 
	pinctrl-0 = <&uart8_tx_pj8 &uart8_rx_pj9>;
	pinctrl-names = "default";
	current-speed = <115200>;
};

// &usart2 {
// 	status = "okay"; 
// 	pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pd6>;
// 	pinctrl-names = "default";
// 	current-speed = <115200>;
// };




/* m7 SDMMC2 node */
&sdmmc2 {
    status = "okay";
    compatible = "st,stm32-sdmmc"; 
	  clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00010000>,
	  		<&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;
    bus-width = <4>; 
    pinctrl-0 = <
        &sdmmc2_d0_pb14
        &sdmmc2_d1_pb15
        &sdmmc2_d2_pb3
        &sdmmc2_d3_pb4
        &sdmmc2_ck_pd6
        &sdmmc2_cmd_pa0
    >;
     pinctrl-names = "default";

    /* 如果沒有 Card Detect，可以移除這行 */
   cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;

    disk-name = "SD";
};

stm32h747i_disco_stm32h747xx_m4.overlay
/*
 * Copyright (c) 2024 Celina Sophie Kalus <[email protected]>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/ {
	chosen {
		zephyr,console = &usart1;
		zephyr,shell-uart = &usart1;
		zephyr,ipc_shm = &sram4;
		zephyr,ipc = &mailbox;
	};
};

&mailbox {
	status = "okay";
};

&usart1 {
	status = "okay";
};
&uart8 {
	status = "disabled";
};


/* m7 SDMMC2 node */
&sdmmc2 {
    status = "okay";
    compatible = "st,stm32-sdmmc"; 
    // clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00010000>,
    // <&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;
    bus-width = <4>; 
    pinctrl-0 = <
        &sdmmc2_d0_pb14
        &sdmmc2_d1_pb15
        &sdmmc2_d2_pb3
        &sdmmc2_d3_pb4
        &sdmmc2_ck_pd6
        &sdmmc2_cmd_pa0
    >;
     pinctrl-names = "default";

    /* 如果沒有 Card Detect，可以移除這行 */
   cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;

    disk-name = "SD";
};


// &clk_hse {
// 	clock-frequency = <DT_FREQ_M(25)>;
// 	status = "okay";
// };

// &clk_hsi48 {
// 	status = "okay";
// };

// &pll {
// 	div-m = <5>;
// 	mul-n = <0xa0>;
// 	div-p = <2>;
// 	div-q = <4>;
// 	div-r = <2>;
// 	clocks = <&clk_hse>;
// 	status = "okay";
// };

// &pll2 {
// 	div-m = <5>;
// 	mul-n = <96>;
// 	div-p = <2>;//ori div-p = <2>;
// 	div-q = <4>;
// 	div-r = <10>;
// 	clocks = <&clk_hse>;  /* Assuming 25MHz HSE */
// 	status = "okay";
// };

[WHMJJ]

Hi Development Team,

We have been trying to log the RCC / PLL / PLL2 clock information, and we noticed that the results on the M4 core are different from those on the M7 core.
According to the M7/M4 initialization flow, the synchronization issue during boot (ref: #86494
) should already be resolved by the patch.

However, we are still encountering an issue where the M4 clock configuration appears incorrect, which leads to SDMMC2 initialization failure.
We attempted to configure the same clock settings in the M4 overlay, but SDMMC2 still fails to initialize, reporting a clock-enable failure.

Is there anything we might be missing in the configuration?
Any guidance would be greatly appreciated.

Thank you.

[FRASTM]

Hi @WHMJJ
Can you please check the device tree of your overlay.
In the stm32H7, the dtsi gives

&sdmmc2 {
			clocks = <&rcc STM32_CLOCK(AHB2, 9U)>,
				 <&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;