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| 1 | +\documentclass[8pt]{article} |
| 2 | +\usepackage{amssymb} |
| 3 | +\usepackage{hyperref} |
| 4 | +\usepackage{pgfplots} |
| 5 | +\usepackage{placeins} |
| 6 | +\usepackage{array} |
| 7 | +\usepackage{tikz} |
| 8 | +\usepackage{circuitikz} |
| 9 | +\usetikzlibrary{circuits.logic.US, circuits.ee.IEC, positioning} |
| 10 | +\usepackage{amsmath} |
| 11 | +\usepackage{graphicx} |
| 12 | +\usepackage[T1]{fontenc} |
| 13 | +\usepackage[utf8]{inputenc} |
| 14 | +\usepackage{listings} |
| 15 | +\usepackage{xcolor} |
| 16 | +\usepackage{geometry} |
| 17 | +\input{kvmacros.tex} |
| 18 | +\geometry{margin=0.4in} |
| 19 | + |
| 20 | +\lstdefinelanguage{SystemVerilog}{ |
| 21 | + morekeywords={module, endmodule, logic, bit, int, enum, struct, |
| 22 | + always_ff, always_comb, initial, final, interface, modport, property, |
| 23 | + assert, class, rand, constraint, generate, endgenerate, if, else, begin, end}, |
| 24 | + sensitive=true, |
| 25 | + morecomment=[l]{//}, |
| 26 | + morecomment=[s]{/*}{*/}, |
| 27 | + morestring=[b]", |
| 28 | +} |
| 29 | + |
| 30 | +\lstset{ |
| 31 | + language=SystemVerilog, |
| 32 | + basicstyle=\ttfamily\footnotesize, |
| 33 | + keywordstyle=\color{blue}\bfseries, |
| 34 | + commentstyle=\color{gray}\itshape, |
| 35 | + stringstyle=\color{red}, |
| 36 | + frame=single, |
| 37 | + breaklines=true, |
| 38 | + postbreak=\mbox{\textcolor{red}{$\hookrightarrow$}\space}, |
| 39 | +} |
| 40 | + |
| 41 | +\begin{document} |
| 42 | + |
| 43 | +\begin{itemize} |
| 44 | + \item Setup time $t_{setup}$: time before clock edge that data must be |
| 45 | + stable. |
| 46 | + \item Hold time $t_{hold}$: time after clock edge that data must be stable. |
| 47 | + \item Propagation delay $t_{pcq}$: time after clock edge that output |
| 48 | + is guaranteed to be stable. |
| 49 | + \item Contamination delay $t_{ccq}$: time after clock edge that output |
| 50 | + might be unstable. |
| 51 | +\end{itemize} |
| 52 | + |
| 53 | +\begin{align} |
| 54 | + T_{clk} \geq t_{pcq} + t_{pd} + t_{setup} & \text{Setup Time Constraint} \\ |
| 55 | + t_{hold} < t_{ccq} + t_{cd} & \text{Hold Time Constraint} |
| 56 | +\end{align} |
| 57 | +\end{document} |
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