Skip to content
Closed
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
4 changes: 2 additions & 2 deletions mcu_soc/design/design.py
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
from chipflow_digital_ip.io import SPISignature, SPIPeripheral
from chipflow_digital_ip.io import I2CSignature, I2CPeripheral

from amaranth_cv32e40p.cv32e40p import CV32E40P, DebugModule
from chipflow_digital_ip.processors import CV32E40P, OBIDebugModule
from chipflow_lib.platforms import InputIOSignature, OutputIOSignature
from .ips.pwm import PWMPins, PWMPeripheral
# from .ips.pdm import PDMPeripheral
Expand Down Expand Up @@ -126,7 +126,7 @@ def elaborate(self, platform):
m.submodules.cpu = cpu

# Debug
debug = DebugModule()
debug = OBIDebugModule()
wb_arbiter.add(debug.initiator)
wb_decoder.add(debug.target, name="debug", addr=self.debug_base)
m.d.comb += cpu.debug_req.eq(debug.debug_req)
Expand Down
1 change: 0 additions & 1 deletion pyproject.toml
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,6 @@ license = {file = "LICENSE.md"}
requires-python = ">=3.11"
dependencies = [
"amaranth[builtin-yosys]>=0.5.1",
"amaranth-cv32e40p @ git+https://github.com/ChipFlow/amaranth-cv32e40p",
"chipflow-digital-ip @ git+https://github.com/ChipFlow/chipflow-digital-ip",
"minerva @ git+https://github.com/minerva-cpu/minerva",
"chipflow-lib @ git+https://github.com/ChipFlow/chipflow-lib.git",
Expand Down