Format and typo fixes

Dr-Noob · Sep 6, 2024 · 5a1165c · 5a1165c
1 parent 9df98e5
commit 5a1165c
Show file tree

Hide file tree

Showing 2 changed files with 25 additions and 26 deletions.
diff --git a/src/arm/midr.c b/src/arm/midr.c
@@ -55,12 +55,12 @@ bool read_registry_hklm_int(char* path, char* name, void* value, bool is64) {
   DWORD value_len;
   int reg_type;
   if (is64) {
-	value_len = sizeof(int64_t);
-	reg_type = RRF_RT_REG_QWORD;
+    value_len = sizeof(int64_t);
+    reg_type = RRF_RT_REG_QWORD;
   }
   else {
-	value_len = sizeof(int32_t);
-	reg_type = RRF_RT_REG_DWORD;
+    value_len = sizeof(int32_t);
+    reg_type = RRF_RT_REG_DWORD;
   }
 
   if(RegGetValueA(HKEY_LOCAL_MACHINE, path, name, reg_type, NULL, value, &value_len) != ERROR_SUCCESS) {
@@ -276,27 +276,27 @@ struct features* get_features_info(void) {
   }
   else {
 
-	// FP and AdvSimd are signed. "-1" is the only value that indicates
-	// the feature is not available
+    // FP and AdvSimd are signed. "-1" is the only value that indicates
+    // the feature is not available
 
-	// FP[19:16]
-	// 0: Float support
-	// 1: Float support + FP16
-	int8_t fp = ((int64_t)(pfr0 << (60 - 16)) >> 60);
+    // FP[19:16]
+    // 0: Float support
+    // 1: Float support + FP16
+    int8_t fp = ((int64_t)(pfr0 << (60 - 16)) >> 60);
 
-	// AdvSimd[23:20]
-	// 0: AdvSimd support
-	// 1: AdvSimd support + FP16
-	int8_t adv_simd = ((int64_t)(pfr0 << (60 - 20)) >> 60);
+    // AdvSimd[23:20]
+    // 0: AdvSimd support
+    // 1: AdvSimd support + FP16
+    int8_t adv_simd = ((int64_t)(pfr0 << (60 - 20)) >> 60);
     feat->NEON = (adv_simd >= 0) && (fp >= 0);
 
-	// SVE[35:32]
-  	feat->SVE = (pfr0 >> 32) & 0xF ? true : false;
+    // SVE[35:32]
+    feat->SVE = (pfr0 >> 32) & 0xF ? true : false;
   }
 
-	// Windoes does not expose a registry entry for the ID_AA64ZFR0_EL1 register
-	// this would have mapped to "CP 4024".
-	feat->SVE2 = false;
+  // Windoes does not expose a registry entry for the ID_AA64ZFR0_EL1 register
+  // this would have mapped to "CP 4024".
+  feat->SVE2 = false;
 
   // CP 4030 maps to the ID_AA64ISAR0_EL1 register on Windows
   // https://developer.arm.com/documentation/ddi0601/2024-06/AArch64-Registers/ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0
@@ -306,13 +306,13 @@ struct features* get_features_info(void) {
   }
   else {
     // AES[7:4]
-	feat->AES = (isar0 >> 4) & 0xF ? true : false;
+    feat->AES = (isar0 >> 4) & 0xF ? true : false;
     // SHA1[11:8]
-	feat->SHA1 = (isar0 >> 8) & 0xF ? true : false;
+    feat->SHA1 = (isar0 >> 8) & 0xF ? true : false;
     // SHA2[15:12]
-	feat->SHA2 = (isar0 >> 12) & 0xF ? true : false;
+    feat->SHA2 = (isar0 >> 12) & 0xF ? true : false;
     // CRC32[19:16]
-	feat->CRC32 = (isar0 >> 16) & 0xF ? true : false;
+    feat->CRC32 = (isar0 >> 16) & 0xF ? true : false;
   }
 #endif  // ifdef __linux__
 

diff --git a/src/common/soc.c b/src/common/soc.c
@@ -80,13 +80,12 @@ void fill_soc(struct system_on_chip* soc, char* soc_name, SOC soc_model, int32_t
 
 VENDOR try_match_soc_vendor_name(char* vendor_name)
 {
-  for(size_t i=0; i < sizeof(soc_trademark_string)/sizeof(soc_trademark_string[0]); i++)
-  {
+  for(size_t i=0; i < sizeof(soc_trademark_string)/sizeof(soc_trademark_string[0]); i++) {
     if(soc_trademark_string[i] && strstr(vendor_name, soc_trademark_string[i]) != NULL) {
       return i;
     }
   }
-	return SOC_VENDOR_UNKNOWN;
+  return SOC_VENDOR_UNKNOWN;
 }
 
 bool match_soc(struct system_on_chip* soc, char* raw_name, char* expected_name, char* soc_name, SOC soc_model, int32_t process) {