feat: update scaled_wave for optimization

ElectronicCats · Feb 17, 2025 · 2399a83 · 2399a83
1 parent f6d7389
commit 2399a83
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Showing 3 changed files with 24 additions and 12 deletions.
diff --git a/src/tt_um_waves.v b/src/tt_um_waves.v
@@ -118,7 +118,7 @@ module tt_um_waves (
         end else if (ena) begin
             if (clk_div >= freq_divider) begin
                 clk_div  <= 0;
-                wave_clk <= ~wave_clk;  // Toggle waveform clock
+                wave_clk <= ~wave_clk;  // Ensure wave_clk toggles
             end else begin
                 clk_div <= clk_div + 1;
             end
@@ -127,6 +127,7 @@ module tt_um_waves (
 
 
 
+
     // UART Receiver
     uart_receiver uart_rx_inst (
         .clk(clk),
@@ -184,10 +185,10 @@ reg [7:0] scaled_wave; // Final 8-bit output
 
 always @(posedge clk or negedge rst_n) begin
     if (!rst_n) begin
-        temp_wave <= 16'd0;
+        temp_wave  <= 16'd0;
         scaled_wave <= 8'd0;
     end else begin
-        temp_wave <= selected_wave * adsr_amplitude; // Full precision
+        temp_wave <= selected_wave * adsr_amplitude;
         scaled_wave <= temp_wave[15:8] + (temp_wave[7] ? 8'd1 : 8'd0);
     end
 end
@@ -385,8 +386,8 @@ module i2s_transmitter (
             ws         <= 0;
             sd         <= 0;
             bit_counter <= 0;
-            shift_reg  <= 16'd0;
-        end else if (ena) begin
+            shift_reg  <= {data, data};  // Initialize shift register to avoid x values
+        end else begin
             // Generate I2S Serial Clock (sck) at the correct frequency
             if (clk_div == (SCK_DIV - 1)) begin
                 clk_div <= 0;
@@ -399,7 +400,7 @@ module i2s_transmitter (
             if (sck == 0) begin  // Shift data on the falling edge of sck
                 if (bit_counter == 0) begin
                     ws <= ~ws;  // Toggle word select every 16 bits
-                    shift_reg <= {data, data};  // Duplicate 8-bit data for 16-bit format
+                    shift_reg <= {data, data};  // Load new data
                 end else begin
                     shift_reg <= shift_reg << 1;  // Shift left to send MSB first
                 end

diff --git a/test/Makefile b/test/Makefile
@@ -16,8 +16,9 @@ all: $(SIM_BUILD)/sine_table.mem			#
 
 prepare_files: $(SIM_BUILD)/sine_table.mem
 
-$(SIM_BUILD)/sine_table.mem: $(SRC_DIR)/sine_table.mem				#
-	@echo "Copying sine_table.mem to simulation directory..."		
+$(SIM_BUILD)/sine_table.mem: $(SRC_DIR)/sine_table.mem
+	@echo "Copying sine_table.mem to simulation directory..."
+	mkdir -p $(SIM_BUILD)
 	cp $< $@														
 
 else

diff --git a/test/tb.v b/test/tb.v
@@ -46,14 +46,24 @@ module tb;
   // Load Sine Wave LUT from file
   reg [7:0] sine_table [0:127]; // Adjust size based on file contents
   initial begin
+    integer file;
+    file = $fopen("sine_table.mem", "r");
+    if (file == 0) begin
+        $display("ERROR: sine_table.mem not found! Simulation stopped.");
+        $stop;
+    end
+    $fclose(file);
+
+    $display("Loading sine_table.mem...");
     $readmemh("sine_table.mem", sine_table);
   end
 
-  // Reset sequence
+  // Reset and enable sequence
   initial begin
     #100;
-    rst_n = 1;    
-    ena = 1;      
+    rst_n = 1;  // Release reset
+    #50;
+    ena = 1;    // Enable I2S transmitter and waveform generation
 
     #200;
     ui_in = 8'h41;  // Arbitrary input
@@ -80,7 +90,7 @@ module tb;
   endtask
 
   // Test sequence for UART commands & I2S validation
-  reg [3:0] j;  // Frequency selection index
+  reg [3:0] j;  // Changed from integer to reg
   initial begin
     #100;