feat: corrections on the main module and test.py

src/tt_um_waves.v

@@ -25,6 +25,8 @@ module tt_um_waves (
     reg [31:0] freq_divider;
     reg [31:0] clk_div;
 
+    reg [7:0] wave_gen_output;
+
     always @(posedge clk) begin
         if (!rst_n) begin
             clk_div <= 32'd0;
@@ -178,7 +180,6 @@ module tt_um_waves (
     );
 
     // Wave Generator 
-    //wire [7:0] wave_gen_output;
     wave_generator wave_gen_inst (
        .clk(clk),
        .rst_n(rst_n),
@@ -199,18 +200,19 @@ white_noise_generator noise_gen_inst (
 
 
     // Select Waveform Output
-    //wire [7:0] wave_gen_output;
-    reg [7:0] wave_gen_output;
-    always @(*) begin
+    always @(posedge clk) begin
+    if (!rst_n)
+        wave_gen_output <= 8'd0;
+    else begin
         case (wave_select)
-            3'b000: wave_gen_output = tri_wave_out;
-            3'b001: wave_gen_output = saw_wave_out;
-            3'b010: wave_gen_output = sqr_wave_out;
-            3'b011: wave_gen_output = sine_wave_out;
-            default: wave_gen_output = 8'd0;
+            3'b000: wave_gen_output <= tri_wave_out;
+            3'b001: wave_gen_output <= saw_wave_out;
+            3'b010: wave_gen_output <= sqr_wave_out;
+            3'b011: wave_gen_output <= sine_wave_out;
+            default: wave_gen_output <= 8'd0;
         endcase
     end
-
+end
     // Select Waveform
     wire [7:0] selected_wave;
     assign selected_wave = (white_noise_en) ? noise_out : wave_gen_output;
@@ -219,7 +221,6 @@ white_noise_generator noise_gen_inst (
     wire [7:0] scaled_wave;
     assign scaled_wave = (selected_wave * adsr_amplitude) >> 8;
 
-
     // I2S Output
     wire i2s_sck, i2s_ws, i2s_sd;
 

test/test.py

@@ -10,30 +10,30 @@ async def uart_send(dut, data):
 
     # Start bit (low)
     dut.ui_in.value = 0
-    await Timer(104_167, units="ns")  # 9600 baud rate (1 bit = 104.167µs)
+    await ClockCycles(dut.clk, 2604)  # Adjusted for 25MHz clock
 
     # Send 8 data bits (LSB first)
     for i in range(8):
         dut.ui_in.value = (data >> i) & 1
-        await Timer(104_167, units="ns")
+        await ClockCycles(dut.clk, 2604)
 
     # Stop bit (high)
     dut.ui_in.value = 1
-    await Timer(104_167, units="ns")
+    await ClockCycles(dut.clk, 2604)
 
-    # Wait before next command
-    await Timer(1_000_000, units="ns")  # 1 ms delay for processing
+    # Wait before next command (~1ms delay)
+    await ClockCycles(dut.clk, 25000)
 
 @cocotb.test()
 async def test_waveform_generation(dut):
     """ Test UART commands, waveform selection, and I2S output verification. """
 
-    # Start clock (10ns period → 100 MHz)
-    cocotb.start_soon(Clock(dut.clk, 10, units="ns").start())
+    # Start clock (40ns period → 25 MHz)
+    cocotb.start_soon(Clock(dut.clk, 40, units="ns").start())
 
     # Reset DUT
     dut.rst_n.value = 0
-    await ClockCycles(dut.clk, 10)
+    await ClockCycles(dut.clk, 100)  # Longer reset period
     dut.rst_n.value = 1
     dut.ena.value = 1  # Enable module
 
@@ -49,7 +49,7 @@ async def test_waveform_generation(dut):
 
     for cmd, name in wave_commands.items():
         await uart_send(dut, ord(cmd))
-        await ClockCycles(dut.clk, 500)  # Allow processing time
+        await ClockCycles(dut.clk, 1000)  # Allow processing time
 
         # Observe I2S serial data (uo_out[2]) change
         i2s_sd_before = dut.uo_out[2].value
@@ -64,7 +64,7 @@ async def test_waveform_generation(dut):
     # Test UART: Set frequency (sending '0' - '9')
     for i in range(10):
         await uart_send(dut, ord(str(i)))
-        await ClockCycles(dut.clk, 500)  # Allow processing time
+        await ClockCycles(dut.clk, 1000)  # Allow processing time
 
         # Observe I2S clock (uo_out[0]) toggles
         prev_sck = dut.uo_out[0].value
@@ -78,7 +78,7 @@ async def test_waveform_generation(dut):
 
     # Test UART: Enable White Noise ('N') and Disable ('F')
     await uart_send(dut, ord('N'))
-    await ClockCycles(dut.clk, 500)
+    await ClockCycles(dut.clk, 1000)
 
     # Observe randomness in I2S serial data (uo_out[2])
     i2s_noise_before = dut.uo_out[2].value
@@ -91,7 +91,7 @@ async def test_waveform_generation(dut):
     assert i2s_noise_before != i2s_noise_after, "White noise selection failed (I2S SD signal did not change)"
 
     await uart_send(dut, ord('F'))
-    await ClockCycles(dut.clk, 500)
+    await ClockCycles(dut.clk, 1000)
 
     # Observe I2S serial data (uo_out[2]) again
     i2s_noise_off_before = dut.uo_out[2].value
@@ -107,16 +107,16 @@ async def test_waveform_generation(dut):
     await ClockCycles(dut.clk, 1000)  # Ensure stability
     dut._log.info("Checking I2S outputs...")
 
-    sck = dut.uo_out[0].value
-    ws = dut.uo_out[1].value
-    sd = dut.uo_out[2].value
+    # Ensure SCK, WS, and SD toggle
+    prev_sck, prev_ws, prev_sd = dut.uo_out[0].value, dut.uo_out[1].value, dut.uo_out[2].value
+    await ClockCycles(dut.clk, 100)
 
-    dut._log.info(f"I2S Signals -> SCK: {sck}, WS: {ws}, SD: {sd}")
+    new_sck, new_ws, new_sd = dut.uo_out[0].value, dut.uo_out[1].value, dut.uo_out[2].value
 
-    assert sck in [0, 1], "I2S SCK signal incorrect"
-    assert ws in [0, 1], "I2S WS signal incorrect"
-    assert sd in [0, 1], "I2S SD signal incorrect"
+    assert prev_sck != new_sck, "I2S SCK did not toggle"
+    assert prev_ws != new_ws, "I2S WS did not toggle"
+    assert prev_sd != new_sd, "I2S SD did not toggle"
 
-    dut._log.info("I2S signals verified")
+    dut._log.info("I2S signal toggling verified successfully.")
 
     dut._log.info("All tests passed successfully!")