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feat: update bits used by square wave
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Elizabeth-0 committed Feb 28, 2025
1 parent 79eaf29 commit 53ecf6a
Showing 1 changed file with 10 additions and 9 deletions.
19 changes: 10 additions & 9 deletions src/tt_um_waves.v
Original file line number Diff line number Diff line change
Expand Up @@ -631,24 +631,25 @@ endmodule



module triangular_wave_generator (
input wire ena,
input wire clk,
input wire rst_n,
input wire [7:0] phase,
output reg [7:0] wave_out
);
module square_wave_generator (
input wire ena, // Enable signal
input wire clk, // Clock signal
input wire rst_n, // Active-low reset signal
input wire [7:0] phase, // 8-bit phase input
output reg [7:0] wave_out // 8-bit output wave
);

always @(posedge clk or negedge rst_n) begin
if (!rst_n)
wave_out <= 8'd0;
wave_out <= 8'd0; // Reset output on reset
else if (ena)
wave_out <= phase[7] ? (8'd255 - {1'b0, phase[6:0]} << 1) : ({1'b0, phase[6:0]} << 1);
wave_out <= phase[7] ? 8'd255 : 8'd0; // Use the most significant bit of phase
end
endmodule




module encoder #(
parameter integer WIDTH = 8, // Counter width
parameter integer INCREMENT = 1, // Increment value (must be integer)
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