Add support for Vector context save support on RISC-V

[cubidesj]

Save the vector context when changing the task

Description

An approach similar to #1250 has been used:

• Add the storage for the vector context next to the FPU context
• Enable the VPU as part of the task stack preparation
• Use the VS flags and values to avoid saving and restoring the context
• Save the 32 vector registers, vl, vtype, vstart and vcsr
  • The 32 vector registers are saved/restored according to the configured length

Test Steps

A separate PR in the FreeRTOS repository will be created. That PR contains an enhanced RegTest that includes the vector registers.

Checklist:

• [ X ] I have tested my changes. No regression in existing tests.
• [ X ] I have modified and/or added unit-tests to cover the code changes in this Pull Request.

Related Issue

An approach similar to #1250 was followed. I'll link the corresponding PR with the Demo once it is created

By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.

[cubidesj]

Associated PR in FreeRTOS repo FreeRTOS/FreeRTOS#1334

[codecov]

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 91.53%. Comparing base (60f34f8) to head (5b1a05f).
Report is 6 commits behind head on main.

Additional details and impacted files

@@            Coverage Diff             @@
##             main    #1260      +/-   ##
==========================================
- Coverage   91.59%   91.53%   -0.06%     
==========================================
  Files           6        6              
  Lines        3259     3261       +2     
  Branches      902      904       +2     
==========================================
  Hits         2985     2985              
  Misses        132      132              
- Partials      142      144       +2     

Flag	Coverage Δ
unittests	91.53% <ø> (-0.06%)	⬇️

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[kstribrnAmzn]

The codecov/project workflow is failing (link) due to assertions added in this PR. This is unrelated to this code change and can be ignored.

Coverage can be fixed in a separate PR.

[aggarg]

The current context save code clobbers the saved vstart and vcsr registers when mcause and epc are saved. This results in vstart and vcsr registers getting programmed to incorrect value when context is restored. The following patch address this issue and contains some other minor suggestions: 0001-Code-review-suggestions.patch. Please apply this patch and refresh from the upstream main.

[cubidesj]

Thanks for your suggestions @aggarg. I applied your patch.

[aggarg]

Thank you @cubidesj ! Please refresh from upstream main branch to enable us to merge this PR.

[sonarqubecloud]

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud