Skip to content

[SPIR-V] Promote arbitrary width ints to regular width #249

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
michalpaszkowski wants to merge 1 commit into
base: feature/spirv-backend-llvm15_0_7_2
Choose a base branch
from
Open

[SPIR-V] Promote arbitrary width ints to regular width #249

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
10 changes: 10 additions & 0 deletions llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -80,6 +80,16 @@ SPIRVType *SPIRVGlobalRegistry::getOpTypeBool(MachineIRBuilder &MIRBuilder) {
SPIRVType *SPIRVGlobalRegistry::getOpTypeInt(uint32_t Width,
MachineIRBuilder &MIRBuilder,
bool IsSigned) {
assert(Width <= 64 && "Unsupported integer width!");
if (Width <= 8)
Width = 8;
else if (Width <= 16)
Width = 16;
else if (Width <= 32)
Width = 32;
else if (Width <= 64)
Width = 64;

auto MIB = MIRBuilder.buildInstr(SPIRV::OpTypeInt)
.addDef(createTypeVReg(MIRBuilder))
.addImm(Width)
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,8 @@ unsigned SPIRVTargetLowering::getNumRegistersForCallingConv(
(VT.getVectorElementType() == MVT::i1 ||
VT.getVectorElementType() == MVT::i8))
return 1;
if (!VT.isVector() && VT.isInteger() && VT.getSizeInBits() <= 64)
return 1;
return getNumRegisters(Context, VT);
}

Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1189,6 +1189,7 @@ bool SPIRVInstructionSelector::selectConst(Register ResVReg,
.addUse(GR.getSPIRVTypeID(ResType))
.constrainAllUses(TII, TRI, RBI);
if (TyOpcode == SPIRV::OpTypeInt) {
assert(Imm.getBitWidth() <= 64 && "Unsupported integer width!");
Register Reg = GR.getOrCreateConstInt(Imm.getZExtValue(), I, ResType, TII);
if (Reg == ResVReg)
return true;
Expand Down
19 changes: 7 additions & 12 deletions llvm/lib/Target/SPIRV/SPIRVUtils.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -77,24 +77,19 @@ std::string getStringImm(const MachineInstr &MI, unsigned StartIndex) {

void addNumImm(const APInt &Imm, MachineInstrBuilder &MIB) {
const auto Bitwidth = Imm.getBitWidth();
switch (Bitwidth) {
case 1:
break; // Already handled.
case 8:
case 16:
case 32:
if (Bitwidth == 1)
return; // Already handled
else if (Bitwidth <= 32) {
MIB.addImm(Imm.getZExtValue());
break;
case 64: {
return;
} else if (Bitwidth <= 64) {
uint64_t FullImm = Imm.getZExtValue();
uint32_t LowBits = FullImm & 0xffffffff;
uint32_t HighBits = (FullImm >> 32) & 0xffffffff;
MIB.addImm(LowBits).addImm(HighBits);
break;
}
default:
report_fatal_error("Unsupported constant bitwidth");
return;
}
report_fatal_error("Unsupported constant bitwidth");
}

void buildOpName(Register Target, const StringRef &Name,
Expand Down
58 changes: 58 additions & 0 deletions llvm/test/CodeGen/SPIRV/constant/local-arbitrary-width-integers-constants-type-promotion.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s

define i4 @getConstantI4() {
ret i4 2 ; i4 => OpTypeInt 8
}

define i11 @getConstantI11() {
ret i11 7 ; i11 => OpTypeInt 16
}

define i24 @getConstantI24() {
ret i24 42 ; i24 => OpTypeInt 32
}

define i63 @getConstantI63() {
ret i63 5705 ; i63 => OpTypeInt 64
}

;; Capabilities:
; CHECK-DAG: OpCapability Int8
; CHECK-DAG: OpCapability Int16
; CHECK-DAG: OpCapability Int64

; CHECK-NOT: DAG-FENCE

;; Names:
; CHECK-DAG: OpName %[[#GET_I4:]] "getConstantI4"
; CHECK-DAG: OpName %[[#GET_I11:]] "getConstantI11"
; CHECK-DAG: OpName %[[#GET_I24:]] "getConstantI24"
; CHECK-DAG: OpName %[[#GET_I63:]] "getConstantI63"

; CHECK-NOT: DAG-FENCE

;; Types and Constants:
; CHECK-DAG: %[[#I8:]] = OpTypeInt 8 0
; CHECK-DAG: %[[#I16:]] = OpTypeInt 16 0
; CHECK-DAG: %[[#I32:]] = OpTypeInt 32 0
; CHECK-DAG: %[[#I64:]] = OpTypeInt 64 0
; CHECK-DAG: %[[#CST_I8:]] = OpConstant %[[#I8]] 2
; CHECK-DAG: %[[#CST_I16:]] = OpConstant %[[#I16]] 7
; CHECK-DAG: %[[#CST_I32:]] = OpConstant %[[#I32]] 42
; CHECK-DAG: %[[#CST_I64:]] = OpConstant %[[#I64]] 5705

; CHECK: %[[#GET_I4]] = OpFunction %[[#I8]]
; CHECK: OpReturnValue %[[#CST_I8]]
; CHECK: OpFunctionEnd

; CHECK: %[[#GET_I11]] = OpFunction %[[#I16]]
; CHECK: OpReturnValue %[[#CST_I16]]
; CHECK: OpFunctionEnd

; CHECK: %[[#GET_I24]] = OpFunction %[[#I32]]
; CHECK: OpReturnValue %[[#CST_I32]]
; CHECK: OpFunctionEnd

; CHECK: %[[#GET_I63]] = OpFunction %[[#I64]]
; CHECK: OpReturnValue %[[#CST_I64]]
; CHECK: OpFunctionEnd
12 changes: 12 additions & 0 deletions llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,9 @@
; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s

define i8 @getConstantI8() {
ret i8 2
}

define i16 @getConstantI16() {
ret i16 -58
}
Expand All @@ -17,12 +21,14 @@ define i64 @getLargeConstantI64() {
}

;; Capabilities:
; CHECK-DAG: OpCapability Int8
; CHECK-DAG: OpCapability Int16
; CHECK-DAG: OpCapability Int64

; CHECK-NOT: DAG-FENCE

;; Names:
; CHECK-DAG: OpName %[[#GET_I8:]] "getConstantI8"
; CHECK-DAG: OpName %[[#GET_I16:]] "getConstantI16"
; CHECK-DAG: OpName %[[#GET_I32:]] "getConstantI32"
; CHECK-DAG: OpName %[[#GET_I64:]] "getConstantI64"
Expand All @@ -31,14 +37,20 @@ define i64 @getLargeConstantI64() {
; CHECK-NOT: DAG-FENCE

;; Types and Constants:
; CHECK-DAG: %[[#I8:]] = OpTypeInt 8 0
; CHECK-DAG: %[[#I16:]] = OpTypeInt 16 0
; CHECK-DAG: %[[#I32:]] = OpTypeInt 32 0
; CHECK-DAG: %[[#I64:]] = OpTypeInt 64 0
; CHECK-DAG: %[[#CST_I8:]] = OpConstant %[[#I8]] 2
; CHECK-DAG: %[[#CST_I16:]] = OpConstant %[[#I16]] 65478
; CHECK-DAG: %[[#CST_I32:]] = OpConstant %[[#I32]] 42
; CHECK-DAG: %[[#CST_I64:]] = OpConstant %[[#I64]] 123456789 0
; CHECK-DAG: %[[#CST_LARGE_I64:]] = OpConstant %[[#I64]] 0 8

; CHECK: %[[#GET_I8]] = OpFunction %[[#I8]]
; CHECK: OpReturnValue %[[#CST_I8]]
; CHECK: OpFunctionEnd

; CHECK: %[[#GET_I16]] = OpFunction %[[#I16]]
; CHECK: OpReturnValue %[[#CST_I16]]
; CHECK: OpFunctionEnd
Expand Down