Rename and simplify the RTL project

README.md

@@ -1,21 +1,20 @@
-# Edge AI RTL Lab
+# INT8 Dot-Product RTL
 
-I built Edge AI RTL Lab as a small, reproducible hardware-design project that
-connects quantized AI inference arithmetic with an RTL verification workflow.
-The core computes a signed int8 vector dot product using one multiply-accumulate
-lane, then clamps
-the exact internal sum to a signed output width.
+This project started while I was learning how signed INT8 inference arithmetic
+maps to RTL. It contains one vector dot-product core, a bit-exact Python model,
+a self-checking testbench, and Yosys checks. The core uses one
+multiply-accumulate lane, then clamps the exact internal sum to a signed output
+width.
 
-I kept the scope deliberately small: parameterized SystemVerilog, ready/valid
-control, a bit-exact Python reference model, deterministic regression, and CI.
-This is **not** a trained AI model or a complete neural-network accelerator.
+The small scope is intentional. This is one verified arithmetic block, not a
+trained model, a complete neural-network accelerator, or a silicon result.
 
 <p align="center">
   <img src="assets/rtl-ci-transcript.svg" width="100%" alt="Successful public CI transcript: Icarus Verilog passed deterministic vectors at lengths 1, 8, and 17, and Yosys found no structural problems">
 </p>
 
 This transcript comes from successful public
-[GitHub Actions run 30224621114](https://github.com/Labeeb2339/edge-ai-rtl-lab/actions/runs/30224621114)
+[GitHub Actions run 30224621114](https://github.com/Labeeb2339/int8-dot-product-rtl/actions/runs/30224621114)
 at commit `6fd552b`. The checked-in receipt can be regenerated from the run log
 with `python tools/capture_ci_receipt.py`; the SVG renderer consumes that
 receipt instead of inventing a result.

model/__init__.py

@@ -1,2 +1,2 @@
-"""Reference models for the Edge AI RTL Lab."""
+"""Reference models for the INT8 dot-product RTL project."""
 

tools/capture_ci_receipt.py

@@ -10,7 +10,7 @@
 from pathlib import Path
 
 ROOT = Path(__file__).resolve().parents[1]
-REPOSITORY = "Labeeb2339/edge-ai-rtl-lab"
+REPOSITORY = "Labeeb2339/int8-dot-product-rtl"
 DEFAULT_RUN_ID = 30224621114
 
 
@@ -55,7 +55,7 @@ def _payload(run_id: int) -> dict[str, object]:
         raise SystemExit("could not recover the Yosys structural-check record")
 
     return {
-        "schema_version": "edge-ai-rtl-lab.ci-receipt.v1",
+        "schema_version": "int8-dot-product-rtl.ci-receipt.v1",
         "repository": REPOSITORY,
         "run_id": metadata["databaseId"],
         "run_url": metadata["url"],

tools/render_readme_assets.py

@@ -44,7 +44,7 @@ def render() -> str:
         )
 
     return f'''<svg xmlns="http://www.w3.org/2000/svg" width="1280" height="620" viewBox="0 0 1280 620" role="img" aria-labelledby="title desc">
-  <title id="title">Edge AI RTL Lab deterministic regression matrix</title>
+  <title id="title">INT8 Dot-Product RTL deterministic regression matrix</title>
   <desc id="desc">Stacked bars show corner and fixed-seed random transactions for vector lengths 1, 8, and 17. A verification panel lists ten Python model tests, Icarus RTL simulation, and a Yosys structural check.</desc>
   <style>
     .title {{ font: 700 34px ui-monospace, SFMono-Regular, Menlo, Consolas, monospace; fill: #13253b; }}
@@ -175,7 +175,7 @@ def map_y(value: int) -> float:
     zero_y = map_y(0)
 
     return f'''<svg xmlns="http://www.w3.org/2000/svg" width="1280" height="650" viewBox="0 0 1280 650" role="img" aria-labelledby="sat-title sat-desc">
-  <title id="sat-title">Edge AI RTL Lab signed 16-bit saturation evidence</title>
+  <title id="sat-title">INT8 Dot-Product RTL signed 16-bit saturation evidence</title>
   <desc id="sat-desc">The clamp transfer curve and six named deterministic vectors show exact accumulator sums mapped to signed 16-bit outputs. Four vectors clamp and two remain exactly on the boundaries.</desc>
   <style>
     .title {{ font: 700 31px ui-monospace, SFMono-Regular, Menlo, Consolas, monospace; fill: #13253b; }}
@@ -225,7 +225,11 @@ def map_y(value: int) -> float:
 
 def render_ci_transcript() -> str:
     receipt = json.loads(CI_RECEIPT.read_text(encoding="utf-8"))
-    if receipt.get("schema_version") != "edge-ai-rtl-lab.ci-receipt.v1":
+    supported_schemas = {
+        "edge-ai-rtl-lab.ci-receipt.v1",
+        "int8-dot-product-rtl.ci-receipt.v1",
+    }
+    if receipt.get("schema_version") not in supported_schemas:
         raise ValueError("unsupported RTL CI receipt schema")
     if receipt.get("conclusion") != "success":
         raise ValueError("RTL CI receipt is not a successful run")
@@ -274,7 +278,7 @@ def render_ci_transcript() -> str:
     run_id = int(receipt["run_id"])
     commit = escape(str(receipt["commit"])[:7])
     return f'''<svg xmlns="http://www.w3.org/2000/svg" width="1280" height="650" viewBox="0 0 1280 650" role="img" aria-labelledby="ci-title ci-desc">
-  <title id="ci-title">Successful Edge AI RTL Lab simulator and synthesis transcript</title>
+  <title id="ci-title">Successful INT8 Dot-Product RTL simulator and synthesis transcript</title>
   <desc id="ci-desc">A terminal-style rendering of GitHub Actions run {run_id}: Icarus Verilog passed all deterministic vectors at vector lengths 1, 8, and 17, and Yosys reported no structural problems.</desc>
   <style>
     .chrome {{ font: 600 15px ui-monospace, SFMono-Regular, Menlo, Consolas, monospace; }}