[https://nvbugs/5527655][feat] Add NUMA-aware CPU affinity autoconfig #8805
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📝 WalkthroughWalkthroughAdds NUMA-aware CPU affinity configuration: new utility to derive CPU sets from NVML and a BaseWorker method that inspects current affinity and applies NUMA-aware affinity during worker rank/device setup; removes prior affinity-clearing logic. Changes
Sequence DiagramsequenceDiagram
participant Worker as Worker Process
participant Base as BaseWorker._get_comm_ranks_device_id
participant GPU as RayGPUWorker._get_comm_ranks_device_id
participant Aff as BaseWorker._configure_affinity
participant Ps as psutil
participant NVML as NVML
participant OS as os.sched_setaffinity
Worker->>GPU: start/init
GPU->>GPU: determine comm_ranks & device_id
GPU->>Aff: _configure_affinity(device_id)
Aff->>Ps: inspect current affinity
Aff->>Aff: is affinity constrained?
alt not constrained and NUMA enabled
Aff->>NVML: get device CPU affinity mask
NVML-->>Aff: mask
Aff->>Aff: convert mask → CPU id list
Aff->>OS: set process affinity to CPU ids
else constrained or NUMA disabled
Aff-->>Aff: log warning / skip setting
end
Aff-->>GPU: done
GPU-->>Worker: continue startup
Estimated code review effort🎯 4 (Complex) | ⏱️ ~45 minutes Areas that need extra attention:
Pre-merge checks and finishing touches❌ Failed checks (2 warnings)
✅ Passed checks (1 passed)
✨ Finishing touches
🧪 Generate unit tests (beta)
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Actionable comments posted: 4
🧹 Nitpick comments (1)
tensorrt_llm/llmapi/utils.py (1)
532-532: Consider moving pynvml import to module level.The
pynvmlimport is placed inside the function, which is unconventional. While this might be intentional to avoid import errors on systems without NVIDIA drivers, it's typically better to import at module level and handle ImportError at the call site if needed.If the lazy-import pattern is not required, apply this diff:
At the top of the file (after line 27):
import pynvmlThen remove line 532 from the function.
Alternatively, if lazy loading is desired, keep the current pattern but add a comment explaining why.
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📒 Files selected for processing (4)
tensorrt_llm/executor/base_worker.py(3 hunks)tensorrt_llm/executor/ray_gpu_worker.py(1 hunks)tensorrt_llm/executor/worker.py(1 hunks)tensorrt_llm/llmapi/utils.py(2 hunks)
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tensorrt_llm/executor/worker.pytensorrt_llm/executor/base_worker.pytensorrt_llm/executor/ray_gpu_worker.pytensorrt_llm/llmapi/utils.py
**/*.{cpp,cxx,cc,h,hpp,hh,hxx,cu,cuh,py}
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🧠 Learnings (2)
📚 Learning: 2025-07-17T09:01:27.402Z
Learnt from: amitz-nv
PR: NVIDIA/TensorRT-LLM#5616
File: tensorrt_llm/executor/worker.py:375-384
Timestamp: 2025-07-17T09:01:27.402Z
Learning: In tensorrt_llm/executor/worker.py, the LoRA adapter cache optimization logic that checks `is_adapter_in_cpu_cache()` and conditionally passes None for weights/config has a known race condition issue that cannot be solved with simple error handling or verification checks. This is a known limitation that requires a more comprehensive solution.
Applied to files:
tensorrt_llm/executor/worker.pytensorrt_llm/executor/base_worker.pytensorrt_llm/executor/ray_gpu_worker.py
📚 Learning: 2025-09-24T03:31:28.908Z
Learnt from: tongyuantongyu
PR: NVIDIA/TensorRT-LLM#7520
File: tensorrt_llm/_torch/pyexecutor/resource_manager.py:605-613
Timestamp: 2025-09-24T03:31:28.908Z
Learning: In TensorRT-LLM Ray orchestrator mode, ProcessGroups are initialized with both Gloo and NCCL backends (e.g., "cuda:nccl,cpu:gloo"), allowing PyTorch distributed to automatically route CPU tensors through Gloo and GPU tensors through NCCL. This eliminates the need for manual device placement when performing allreduce operations on base types.
Applied to files:
tensorrt_llm/executor/ray_gpu_worker.py
🧬 Code graph analysis (3)
tensorrt_llm/executor/worker.py (1)
tensorrt_llm/llmapi/utils.py (4)
AsyncQueue(361-445)ManagedThread(279-329)_SyncQueue(448-515)logger_debug(105-118)
tensorrt_llm/executor/base_worker.py (2)
tensorrt_llm/llmapi/utils.py (3)
get_numa_aware_cpu_affinity(518-549)get(415-445)get(498-515)tensorrt_llm/executor/ray_gpu_worker.py (1)
_get_comm_ranks_device_id(188-200)
tensorrt_llm/executor/ray_gpu_worker.py (1)
tensorrt_llm/executor/base_worker.py (1)
_configure_affinity(97-123)
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🔇 Additional comments (5)
tensorrt_llm/executor/worker.py (1)
21-22: LGTM!The import changes correctly remove the deprecated
clear_sched_affinityand add the necessary utilities for the new queue and logging infrastructure.tensorrt_llm/executor/ray_gpu_worker.py (1)
197-199: LGTM!The affinity configuration is correctly placed after the device IDs are gathered and shared across workers, ensuring each worker can set its affinity based on the correct device.
tensorrt_llm/executor/base_worker.py (2)
5-5: LGTM!The new imports (
os,psutil, andget_numa_aware_cpu_affinity) are all used appropriately in the_configure_affinitymethod.Also applies to: 11-11, 24-24
132-134: LGTM!The affinity configuration is correctly invoked after the device ID is determined and inter-process coordination is complete.
tensorrt_llm/llmapi/utils.py (1)
3-3: LGTM!The new imports (
ctypesandmath) are used appropriately for computing the affinity mask array size and bit manipulation.Also applies to: 8-8
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Do we have any performance numbers to show it actually helps? |
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LGTM overall. Just need to address handling NVML failures as pointed out by coderabbit
I've collected some preliminary numbers, but I'd like to collect numbers from many different launches/runs, since the biggest impact is a reduction in variability, which is hard to assess from comparing even multiple iterations of a benchmark from a single launch of trtllm-serve, for example. I'll update the review with the numbers later today. |
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Here are the performance results. I launched trtllm-serve 3 separate times with each configuration (running sudo sysctl vm.drop_caches=3 in between launches). The test case here is together.ai's original configuration from the bug (no piecewise CUDA graph, since the host overhead is more pronounced without it). Overall, I see ~9% reduction in TTFT and a small, but modest decrease in run-to-run variation (~1%):
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/bot run |
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PR_Github #23398 [ run ] triggered by Bot. Commit: |
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In the default mode, can you add the trtllm-bench comparison between this PR and the main base? Llama 3.1 8B FP8 on H100 HBM3 TP1 should be sufficient. Just hope to double-confirm the default performance just works as expected. |
…uration Signed-off-by: Dan Hansen <[email protected]>
Signed-off-by: Dan Hansen <[email protected]>
… TLLM_NUMA_WORKER_AFFINITY Signed-off-by: Dan Hansen <[email protected]>
Signed-off-by: Dan Hansen <[email protected]>
Signed-off-by: Dan Hansen <[email protected]>
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Here are the results:
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/bot run |
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PR_Github #23671 [ run ] triggered by Bot. Commit: |
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PR_Github #23671 [ run ] completed with state |
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/bot run |
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PR_Github #23688 [ run ] triggered by Bot. Commit: |
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PR_Github #23688 [ run ] completed with state |
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/bot skip --comment "CI already passed" |
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PR_Github #23770 [ skip ] triggered by Bot. Commit: |
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PR_Github #23770 [ skip ] completed with state |
…NVIDIA#8805) Signed-off-by: Dan Hansen <[email protected]> Co-authored-by: Dan Hansen <[email protected]>
Signed-off-by: Dan Hansen <[email protected]> Co-authored-by: Dan Hansen <[email protected]> Signed-off-by: Dan Hansen <[email protected]>
8 participants
Description
New Feature: NUMA-aware CPU affinity autoconfiguration:
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