refactor: Named signals for badStop and fastStart

NYU-Processor-Design · Oct 23, 2023 · 14a4dc7 · 14a4dc7
1 parent 363cd57
commit 14a4dc7
Show file tree

Hide file tree

Showing 2 changed files with 12 additions and 4 deletions.
diff --git a/rtl/UartRx/UartRx.sv b/rtl/UartRx/UartRx.sv
@@ -42,12 +42,16 @@ module UartRx #(
   logic badSync;
   logic reSync;
   logic advance;
+  logic badStop;
+  logic fastStart;
 
   always_comb begin
     edgeDetect = fall || rise;
     badSync = edgeDetect && edgeCmp && (sampleCount >= halfSampleCount);
     reSync = edgeDetect && (sampleCount < halfSampleCount);
     advance = reSync || (sampleCount == 0);
+    badStop = in == 0 && sampleCount == halfSampleCount;
+    fastStart = fall && sampleCount < halfSampleCount;
     done = advance && (readCount == 0);
     err = nextState == ERROR;
   end
@@ -129,9 +133,9 @@ module UartRx #(
       end
 
       STOP:
-      if (badSync || (in == 0 && sampleCount == halfSampleCount)) begin
+      if (badSync || badStop) begin
         nextState = ERROR;
-      end else if (fall && sampleCount < halfSampleCount) begin
+      end else if (fastStart) begin
         nextState = START;
       end else if (advance) begin
         nextState = IDLE;

diff --git a/rtl/UartRx/UartRxEn.sv b/rtl/UartRx/UartRxEn.sv
@@ -43,6 +43,8 @@ module UartRxEn #(
   logic badSync;
   logic reSync;
   logic advance;
+  logic badStop;
+  logic fastStart;
 
   logic [sampleWidth-1:0] sampleCount;
   logic [3:0] readCount;
@@ -54,6 +56,8 @@ module UartRxEn #(
     reSync = edgeDetect && (sampleCount < halfSampleCount);
     advance = reSync || (en && (sampleCount == 0));
     done = advance && (readCount == 0);
+    badStop = en && in == 0 && sampleCount == halfSampleCount;
+    fastStart = en && fall && sampleCount < halfSampleCount;
     err = nextState == ERROR;
   end
 
@@ -130,9 +134,9 @@ module UartRxEn #(
       end
 
       STOP:
-      if (badSync || (en && (in == 0) && (sampleCount == halfSampleCount))) begin
+      if (badSync || badStop) begin
         nextState = ERROR;
-      end else if (en && fall && (sampleCount < halfSampleCount)) begin
+      end else if (fastStart) begin
         nextState = START;
       end else if (advance) begin
         nextState = IDLE;