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Riscv vector state ctx - #7876

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dave-patel-riscstar:riscv-vector-state-ctx
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Riscv vector state ctx#7876
dave-patel-riscstar wants to merge 2 commits into
OP-TEE:masterfrom
dave-patel-riscstar:riscv-vector-state-ctx

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@dave-patel-riscstar

@dave-patel-riscstar dave-patel-riscstar commented Jul 8, 2026

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@github-actions

github-actions Bot commented Jul 8, 2026

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FYI @maroueneboubakri

@dave-patel-riscstar

dave-patel-riscstar commented Jul 8, 2026

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_ No description provided. _

@maroueneboubakri
please find Vector PR

Note: I am able to resolve the CFG_WITH_VFP flag issue, however the implementation of thread has to be moved from thread.c to thread_arch.c as thread.c is common between RISCV and ARM.

so I will make same changes to FP PR as well.

Thanks.

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github-actions Bot commented Aug 8, 2026

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This pull request has been marked as a stale pull request because it has been open (more than) 30 days with no activity. Remove the stale label or add a comment, otherwise this pull request will automatically be closed in 5 days. Note, that you can always re-open a closed issue at any time.

@github-actions github-actions Bot added the Stale label Aug 8, 2026
@dave-patel-riscstar
riscv: core: implement vector context save and restore routines
b7a2a8e 
Introduce a clean assembly implementation for saving and restoring the
floating-point register context into high-performance, pure assembly
within riscv_vector.S.

To optimize context switching performance recursive macros is used
to unroll vector chunk operations (vl8r.v and vs8r.v).

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
@dave-patel-riscstar
core: riscv: add thread support for vector context management
f88d39d 
Add RISC-V thread support for vector state management.

Introduce thread helpers to enable, disable, save and restore vector
state during thread context switches. Store the per-thread vector
context in struct thread_ctx and use the architecture-specific
save/restore routines provided by riscv_vector.S.

Use the existing RISC-V CSR helpers to manipulate sstatus instead of
open-coded CSR accesses, matching the existing OP-TEE coding style.

Signed-off-by: Dave Patel <dave.patel@riscstar.com>
@github-actions github-actions Bot removed the Stale label Aug 11, 2026
@dave-patel-riscstar

dave-patel-riscstar commented Aug 12, 2026

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D/TA: os_test_shlib_init:16 os_test_global=2
D/TA: os_test_init:1383 os_test_global=21
D/TA: TA_CreateEntryPoint:20 TA_CreateEntryPoint
D/TA: TA_OpenSessionEntryPoint:38 TA_OpenSessionEntryPoint
F/TC:? 0 trace_syscall:147 syscall #10 (syscall_unmask_cancellation)
I/TA: TA: Initialising Vector registers with test pattern...
I/TA: Dave TA: Before Context Switch
I/TA: Dave TA: Sleeping for 50ms to force a context switch...
F/TC:? 0 trace_syscall:147 syscall #13 (syscall_get_time)
I/TA: Dave TA: Resumed. Verifying Vector register integrity...
I/TA: Dave TA: After Context Switch
I/TA: Dave TA: SUCCESS! Vector context switch verified perfectly.
D/TC:? 0 tee_ta_close_session:460 csess 0xf10b4a50 id 3
D/TC:? 0 tee_ta_close_session:479 Destroy session
D/TA: TA_CloseSessionEntryPoint:46 TA_CloseSessionEntryPoint
D/TA: TA_DestroyEntryPoint:27 TA_DestroyEntryPoint
D/TC:? 0 destroy_context:318 Destroy TA ctx (0xf10b49f0)

@dave-patel-riscstar

dave-patel-riscstar commented Aug 12, 2026

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TEE test application started over default TEE instance
######################################################

regression

######################################################

  • regression_1046 RISC-V Vector context switching
    regression_1046 OK
    +-----------------------------------------------------
    Result of testsuite regression filtered by "1046":
    regression_1046 OK
    +-----------------------------------------------------
    2 subtests of which 0 failed
    1 test case of which 0 failed
    107 test cases were skipped
    TEE test application done!

@jenswikl

jenswikl commented Aug 13, 2026

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What's that test?

@dave-patel-riscstar

dave-patel-riscstar commented Aug 13, 2026

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What's that test?

Its a context switch test, loading vectors registers do some vector operation, then get time using system call (context switch) and then check the vector registers after to compare with original value and vector registers are successfully restored post syscall.

@jenswikl

jenswikl commented Aug 13, 2026

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Thanks. Do you intend to upstream it? I guess the test could be added to one of our existing TAs.

@dave-patel-riscstar

dave-patel-riscstar commented Aug 13, 2026

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Thanks. Do you intend to upstream it? I guess the test could be added to one of our existing TAs.

yes sure

@dave-patel-riscstar

dave-patel-riscstar commented Aug 27, 2026

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Thanks. Do you intend to upstream it? I guess the test could be added to one of our existing TAs.

OP-TEE/optee_test#827

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@dave-patel-riscstar @jenswikl