add RVV crypto acceleration support - #7967
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Introduce CFG_RISCV_VECTOR and the Zvk extension configuration options. Enable the relevant compiler ISA extensions and enforce the required configuration dependencies only when the corresponding settings are selected. Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Compile C code without automatically enabled vector extensions while keeping the extensions available to explicitly annotated assembly. This prevents compiler-generated vector instructions from running where the vector context has not been prepared. Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Import RISC-V vector AES assembly sources from Linux v7.2, retaining their original filenames, dual Apache-2.0/BSD-2-Clause license notices, and upstream copyright attributions. Adapt only the Linux linkage macros to OP-TEE. Add the OP-TEE crypto_drv key-expansion adapter and select the AES sources with CFG_CORE_CRYPTO_AES_ACCEL. The Linux vector routines use normal encryption round keys for both encryption and decryption, so the adapter provides that schedule for both key buffers. Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
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Adapt AES-XTS vector routine from Linux v7.2 to the OP-TEE crypto_drv interface. Encrypt the raw XTS tweak with the second key, construct Linux-compatible key contexts for the two LibTomCrypt schedules, and invoke the imported ZVKNED/ZVBB/ZVKG assembly. Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Import RISC-V vector SHA-256 and SHA-512 compression routines from Linux v7.2, retaining their original filenames, dual Apache-2.0/BSD-2-Clause license notices, and upstream copyright attributions. Adapt only the Linux linkage macros to OP-TEE. Add OP-TEE crypto_drv glue and select each implementation independently with CFG_CORE_CRYPTO_SHA256_ACCEL and CFG_CORE_CRYPTO_SHA512_ACCEL. Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
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@jenswikl @jforissier @maroueneboubakri Please ignore the remaining false-positive code style checks, those assemblies are imported from Linux v7.2 and should be retained as what they are as possible. |
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This series integrates RISC-V vector crypto extensions into OP-TEE with support for SHA256/512, AES key expansion and AES XTS.
It introduces RISC-V vector/Zvk configuration options, and imports the relevant AES and SHA256/512 vector routines from Linux v7.2. The assembly sources retain their original filenames, SPDX identifiers, and upstream copyright notices; only linkage adaptation needed for OP-TEE is applied.
The series adds:
CFG_RISCV_VECTORandCFG_RISCV_ZVKNGconfiguration handling;CFG_CORE_CRYPTO_SHA256_ACCELandCFG_CORE_CRYPTO_SHA512_ACCEL.This series intentionally does not enable acceleration by default. It requires RISC-V vector proper context save/restore across secure/non-secure transitions, which is in the RISC-V vector context switch series - being submitted by other people independently. Until that is available, the RVV and crypto-acceleration configuration options must remain disabled.
Also, other AES modes (ECB, CBC, CTR) support is required to enable
CFG_CORE_CRYPTO_AES_ACCEL: The imported assembly and glue cover key expansion and XTS, while the generic accelerated AES path additionally requires ECB, CBC, and CTR entry points - Those mode wrappers will be added in a follow-up series beforeCFG_CORE_CRYPTO_AES_ACCELis enabled for production use.