RISC-V SBI MPXY fixes and boot integration

core/arch/riscv/include/sbi_mpxy.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 /*
- * Copyright 2025 NXP
+ * Copyright 2025-2026 NXP
  */
 
 #ifndef __SBI_MPXY_H
@@ -18,6 +18,11 @@
 #define SBI_EXT_MPXY_SEND_MSG_WITHOUT_RESP      0x6
 #define SBI_EXT_MPXY_GET_NOTIFICATION_EVENTS    0x7
 
+/* SET_SHMEM arguments */
+#define SBI_MPXY_SHMEM_DISABLE			ULONG_MAX
+#define SBI_MPXY_SHMEM_FLAG_OVERWRITE		0
+#define SBI_MPXY_SHMEM_FLAG_OVERWRITE_RETURN	1
+
 /* Capabilities available through CHANNEL_CAPABILITY attribute */
 #define SBI_MPXY_CHAN_CAP_MSI			BIT(0)
 #define SBI_MPXY_CHAN_CAP_SSE			BIT(1)
@@ -30,8 +35,10 @@
 
 #include <compiler.h>
 #include <encoding.h>
+#include <limits.h>
 #include <stdint.h>
 #include <sys/cdefs.h>
+#include <tee_api_types.h>
 #include <types_ext.h>
 #include <util.h>
 
@@ -141,8 +148,11 @@ struct sbi_mpxy_notification_data {
 };
 
 /* SBI MPXY */
+int sbi_mpxy_init(void);
+bool sbi_mpxy_is_available(void);
 int sbi_mpxy_get_shmem_size(unsigned long *shmem_size);
 int sbi_mpxy_set_shmem(void);
+int sbi_mpxy_disable_shmem(void);
 int sbi_mpxy_get_channel_ids(uint32_t channel_count, uint32_t *channel_ids);
 int sbi_mpxy_read_attributes(uint32_t channel_id, uint32_t base_attribute_id,
 			     uint32_t attribute_count, void *attribute_buf);
@@ -162,8 +172,27 @@ int sbi_mpxy_get_channel_count(uint32_t *channel_count);
 int
 sbi_mpxy_get_notification_events(uint32_t channel_id,
 				 struct sbi_mpxy_notification_data *notif_data,
+				 unsigned long max_events_data_len,
 				 unsigned long *events_data_len);
+TEE_Result sbi_mpxy_to_tee_result(int sbi_err);
+#endif /*__ASSEMBLER__*/
 
+#else /*!defined(CFG_RISCV_SBI_MPXY)*/
+
+#ifndef __ASSEMBLER__
+#include <stdbool.h>
+
+/* sbi.h may not be available without CFG_RISCV_SBI, use the raw value */
+static inline int sbi_mpxy_init(void)
+{
+	return -2; /* SBI_ERR_NOT_SUPPORTED */
+}
+
+static inline bool sbi_mpxy_is_available(void)
+{
+	return false;
+}
 #endif /*__ASSEMBLER__*/
+
 #endif /*defined(CFG_RISCV_SBI_MPXY)*/
 #endif /*__SBI_MPXY_H*/

core/arch/riscv/include/sbi_mpxy_rpmi.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: BSD-2-Clause */
 /*
- * Copyright 2025 NXP
+ * Copyright 2025-2026 NXP
  */
 
 #ifndef __SBI_MPXY_RPMI_H
@@ -87,6 +87,12 @@ struct sbi_mpxy_rpmi_channel {
 	struct sbi_mpxy_channel_attrs attrs;
 	struct sbi_mpxy_rpmi_channel_attrs rpmi_attrs;
 	struct sbi_mpxy_notification_data *notif;
+#if defined(CFG_RISCV_SBI_MPXY_RPMI_MSI)
+	/* Notification state, see sbi_mpxy_rpmi_msi.c */
+	bool have_events_state;
+	bool started;
+	uint32_t msi_irq;
+#endif
 };
 
 /* An instance of RPMI-over-MPXY channel group */
@@ -157,5 +163,14 @@ int sbi_mpxy_rpmi_read_attributes(struct sbi_mpxy_rpmi_channel *channel);
 int sbi_mpxy_rpmi_send_data(struct sbi_mpxy_rpmi_channel *channel, void *data);
 
 #endif /*__ASSEMBLER__*/
+
+#else /*!defined(CFG_RISCV_SBI_MPXY_RPMI)*/
+
+#ifndef __ASSEMBLER__
+static inline void sbi_mpxy_rpmi_probe_channels(void)
+{
+}
+#endif /*__ASSEMBLER__*/
+
 #endif /*defined(CFG_RISCV_SBI_MPXY_RPMI)*/
 #endif /*__SBI_MPXY_RPMI_H*/

core/arch/riscv/kernel/boot.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: BSD-2-Clause
 /*
  * Copyright (c) 2023 Andes Technology Corporation
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2023, 2026 NXP
  */
 
 #include <assert.h>
@@ -25,6 +25,8 @@
 #include <riscv.h>
 #include <rng_support.h>
 #include <sbi.h>
+#include <sbi_mpxy.h>
+#include <sbi_mpxy_rpmi.h>
 #include <stdalign.h>
 #include <stdio.h>
 #include <trace.h>
@@ -245,6 +247,9 @@ void __weak boot_init_primary_runtime(void)
 	boot_primary_init_core_ids();
 	init_tee_runtime();
 	boot_mem_release_tmp_alloc();
+
+	if (!sbi_mpxy_init())
+		sbi_mpxy_rpmi_probe_channels();
 }
 
 void __weak boot_init_primary_final(void)
@@ -273,6 +278,7 @@ static void init_secondary_helper(void)
 
 	thread_init_per_cpu();
 	boot_secondary_init_intc();
+	sbi_mpxy_init();
 
 	IMSG("Secondary CPU%zu (hart%"PRIu32") initialized",
 	     pos, thread_get_hartid());