ta: qcom_pas: anti-rollback enforcement and multi-root certificate selection

core/arch/arm/plat-qcom/hoya/lemans/target.mk

@@ -7,10 +7,6 @@ ifneq ($(CFG_INSECURE),y)
 CFG_QCOM_QFPROM_FUSEPROV ?= y
 endif
 
-ifeq ($(CFG_QCOM_QFPROM_FUSEPROV),y)
-$(call force,CFG_QCOM_QFPROM,y)
-endif
-
 CFG_QCOM_PAS_PTA ?= y
 
 ifeq ($(CFG_QCOM_PAS_PTA),y)
@@ -20,7 +16,22 @@ ifeq ($(CFG_QCOM_PAS_PTA),y)
 CFG_RESERVED_VASPACE_SIZE ?= (256 * 1024 * 1024)
 CFG_IN_TREE_EARLY_TAS += qcom_pas/cff7d191-7ca0-4784-af13-48223b9a4fbe
 CFG_QCOM_PAS_AUTH ?= y
-CFG_PAS_MD_SLOTS = 8
 endif
 
 CFG_QCOM_HWKM ?= y
+
+ifeq ($(CFG_QCOM_PAS_AUTH),y)
+$(call force,CFG_QCOM_FUSE_PTA,y)
+CFG_PAS_MD_SLOTS = 8
+# This chip's OEM_CONFIG2 fuse row has a per-root-cert hash function
+# select bit; targets without it always use SHA-384.
+$(call force,CFG_QCOM_SEGMENT_HASH_SELECT,y)
+# OEM-provisioned multi-root-certificate activation/revocation bitmaps,
+# blown to fuses at boot. 0 (default) provisions nothing.
+CFG_QCOM_MRC_ACTIVATION_LIST ?= 0
+CFG_QCOM_MRC_REVOCATION_LIST ?= 0
+endif
+
+ifneq ($(filter y,$(CFG_QCOM_QFPROM_FUSEPROV) $(CFG_QCOM_FUSE_PTA)),)
+$(call force,CFG_QCOM_QFPROM,y)
+endif

core/drivers/qcom/qfprom/lemans/qfprom_target.h

@@ -17,6 +17,57 @@
 #define QFPROM_CORR_BASE                        0x00784000
 #define QFPROM_SIZE                             0x4000
 
+#define SECURE_BOOT_APPS_OFFSET			0x606c
+#define SECURE_BOOT_AUTH_EN_BMSK		BIT(5)
+#define SECURE_BOOT_USE_SERIAL_NUM_BMSK		BIT(6)
+#define SECURE_BOOT_PK_HASH_IN_FUSE_BMSK	BIT(4)
+
+#define QFPROM_ROOT_OF_TRUST_BYTE_SIZE		48
+
+#define PK_HASH0_SENSE_OFFSET			0x6190
+
+#define PIL_ARB_EN_OFFSET			0x01bc
+#define PIL_ARB_EN_BMSK				0x00000004
+#define PIL_ARB_LSB_OFFSET			0x0278
+#define PIL_ARB_LSB_BMSK			0xffffffff
+#define PIL_ARB_MSB_OFFSET			0x027c
+#define PIL_ARB_MSB_BMSK			0x0fffffff
+#define PIL_ARB_MSB_ENABLED			1
+#define PIL_ARB_RAW_ADDR			(QFPROM_RAW_BASE + 0x0278)
+#define PIL_ARB_LSB_MAX_VERSION			32
+#define PIL_ARB_MSB_MAX_VERSION			28
+
+#define OEM_ID_SENSE_OFFSET			0x6138
+#define OEM_ID_BMSK				GENMASK_32(31, 16)
+#define OEM_ID_SHFT				16
+#define MODEL_ID_BMSK				GENMASK_32(15, 0)
+#define MODEL_ID_SHFT				0
+#define JTAG_ID_SENSE_OFFSET			0x6130
+#define JTAG_ID_AUTH_BMSK			GENMASK_32(27, 0)
+#define SERIAL_NUM_SENSE_OFFSET			0x6134
+
+#define TCSR_SOC_HW_VERSION_ADDR		0x01FC8000
+#define SOC_HW_VERSION_FAM_DEV_BMSK		0xffff0000
+#define SOC_HW_VERSION_FAM_DEV_SHFT		16
+
+#define OEM_CONFIG2_OFFSET			0x6054
+#define EKU_ENFORCEMENT_EN_SHFT			30
+
+#define SEGMENT_HASH_FUNCTION_SELECT0_SHFT	16
+
+#define OEM_CONFIG0_OFFSET			0x604c
+#define ROOT_CERT_TOTAL_NUM_BMSK		0x00060000
+#define ROOT_CERT_TOTAL_NUM_SHFT		17
+#define MRC_ACTIVATION_LIST_OFFSET		0x6268
+#define MRC_REVOCATION_LIST_OFFSET		0x6270
+#define MRC_ROOT_CERT_LIST_BMSK			0x0000000f
+
+#define MRC_ACTIVATION_LIST_RAW_ADDR		(QFPROM_RAW_BASE + 0x0148)
+#define MRC_REVOCATION_LIST_RAW_ADDR		(QFPROM_RAW_BASE + 0x0150)
+
+#define MRC_STICKY_BIT_OFFSET			0x61f0
+#define MRC_STICKY_BIT_BMSK			BIT(3)
+
 #define QFPROM_BLOW_TIMER_OFFSET                0x2030
 #define QFPROM_ACCEL_OFFSET                     0x2038