Releases: OSVVM/OsvvmLibraries
2026.01
Release notes for 2026.01
CoSim
- Adds CoSimPCIe Verification Component - Thanks to Simon Southwell
MIT
- Added DoDirectiveTransactions (AddressBus and Stream) to implement common directive transactions
- Added VHDL-2019 interface capability to AddressBus.
- Support for interfaces in Stream deferred to later revision due to vendor support issues in many simulators.
AXI4 Full VC
- Added VHDL-2019 interfaces
- Architectures are now separate from the entity in Axi4Manager_a.vhd, Axi4Subordinate_a.vhd, and Axi4Memory_a.vhd
- If you need to update architectures, only update the 2019 architecture (in src) and enable TCL variable OsvvmDevDeriveArchitectures "true" in OsvvmSettingsLocal.tcl
ScoreboardGenericPkg
- Updated FindAndFlush and FindAndDelete s.t. if the item is found, it reports as a PASSED and otherwise as FAILED
TestCase Reports
- Opening VHDL Test Case File in vscode, in OsvvmSettingsLocal.tcl set:
variable VhdlFileViewerPrefix "vscode://file/" ;- Default, view in browser
- Assumption, test case file is the one compiled just before simulate
- For VHDL-2019 simulators, integrate VHDL Assert counts into test pass/fail and Alert reporting (AlertLogPkg)
Language Support Package
- Added Constant: TOOL_USES_32_BIT_INTEGERS
Updated build error handling
- By default OSVVM catches all errors and ending with a Tcl error is off.
- This is desirable as when running CI, you want all test cases that can run to run.
- When running CI, use the JUnit test reporter to generate pass/fail messages
- Add the following tcl variables to your OsvvmSettingsLocal.tcl to adjust TCL error signaling:
- FailOnBuildErrors - Signal a tcl error if an error was signaled during a build. Default is false.
- FailOnReportErrors -Signal a tcl error if an error was signaled during reporting. Default is false.
- FailOnTestCaseErrors - Signal a tcl error any test case fails during a build. Default is false.
- AnalyzeErrorStopCount - if 0, do not signal Analyze errors, otherwise, signal analyze error (and stop) when AnalyzeErrorStopCount errors occur. Default is 0.*
- SimulateErrorStopCount - if 0, do not signal Simulate errors, otherwise, signal simulate error (and stop) when SimulateErrorStopCount errors occur. Default is 0*
- If you have errors in any part of the OSVVM process, adjust the following TCL variables
- TclDebug - When true and an OSVVM API command fails, print Tcl's $::errorInfo when an error occurs. Default false.
- ReportDebug - When true and OSVVM reporting fails, print Tcl's $::errorInfo when an error occurs. Default false.
Note
SetInteractiveMode will change both AnalyzeErrorCount and SimulateErrorCount to 1 and Debug to true (which the same impact as TclDebug).
Build Reporting
- If TestSuite has 0, 0, 0 => status is EMPTY
- If compile before fails, do not start the test case.
- Simulate error handling
- IF compile before fails, do not start. Use error message as message to YAML to display
- If simulate fails, use error message to YAML to display.
- If analyze fails before simulate, test case will FAIL and report Analyze Failed
Compile Lists as TOML and CSV List
- CreateDryRunDict - Instead of running analyze and simulate, collect file list and simulate list as dictionaries.
- CreateAnalyzeListCsv - Run in DryRun and produce a inorder CSV list of files
- Closes OSVVM/OSVVM-Scripts#62
- CreateVhdlLsToml - Run in DryRun and produce VHDL LS Toml files.
- Closes OSVVM/OSVVM-Scripts#72
SPI
- Updated SPI test suite so that it is passing again
Scripts
- Added VHDL-2019 feature controls. These are set automatically in the
VendorScripts_***.tclfile. - SetVHDLVersion 2019 automatically done for tools that support it.
- Turn off by doing SetVHDLVersion 2008 in your
OsvvmSettingsLocal.tcl
- Turn off by doing SetVHDLVersion 2008 in your
Report Stuff
- Yaml updates to better collaborate with https://github.com/edaa-org/pyEDAA.OSVVM
2025.06a
This release contains all important artifacts created by OSVVM's CI pipeline.
OSVVM 2025.06a
All Git repositories and submodules have been packaged in a single zip file. This file contains the following
OSVVM components.
Core Components
Verification Components
Third-Party Verification Components
Scripting
Documentation
Published from OSVVM Regression Testing workflow triggered by @JimLewis on 2025-09-21 23:07:07 UTC.
2025.06
Warning
The scripts in this release have some issues. Please use 2025.06a instead.
This release contains all important artifacts created by OSVVM's CI pipeline.
OSVVM 2025.06
All Git repositories and submodules have been packaged in a single zip file. This file contains the following
OSVVM components.
Core Components
Verification Components
Third-Party Verification Components
Scripting
Documentation
Published from OSVVM Regression Testing workflow triggered by @JimLewis on 2025-07-19 03:16:49 UTC.
2025.04
This release contains all important artifacts created by OSVVM's CI pipeline.
OSVVM 2025.04
All Git repositories and submodules have been packaged in a single zip file. This file contains the following
OSVVM components.
Core Components
Verification Components
Third-Party Verification Components
Scripting
Documentation
Published from OSVVM Regression Testing workflow triggered by @JimLewis on 2025-05-06 07:36:21 UTC.
2025.02
This release contains all important artifacts created by OSVVM's CI pipeline.
OSVVM 2025.02
All Git repositories and submodules have been packaged in a single zip file. This file contains the following
OSVVM components.
Core Components
Verification Components
Third-Party Verification Components
Scripting
Documentation
Published from OSVVM Regression Testing workflow triggered by @JimLewis on 2025-02-26 18:25:37 UTC.
2024.07 Release
The 2024.07 release adds:
- Breaking changes in Test Status and CreateClock
- To maintain backward compabitility, set the script variable OsvvmVersionCompatibility to a value 2024.05 or less in OsvvmSettingsLocal.tcl.
- OSVVM provides OsvvmSettingsLocal_example.tcl that can be used to create your OsvvmSettingsLocal.tcl
- AlertLogPkg and TbUtilPkg below show individual ways to override these.
- Note however, if you used selected paths to these procedures, it is a breaking change as the paths have changed from "OSVVM.TbUtilPkg.CreateClock" to "OSVVM.CreateClockPkg.CreateClock"
- Note there are also breaking changes related to TbUtilPkg and named association of Polarity input. See TbUtilPkg below for details.
- AlertLogPkg
- Test Status now reports as: PASSED, FAILED, NOCHECKS, TIMEOUT.
- By default status NOCHECKS is FAILED. Set script variable FailOnNoChecks to false in OsvvmSettingsLocal.tcl to make it PASSED (old behavior)
- PathTail now adds generate label to the name it creates.
- TbUtilPkg
- Added predefined barrier signals: OsvvmTestInit, OsvvmResetDone, OsvvmTestDone, TestDone, OsvvmVcInit
- All procedures that have a Clk input now have a ClkActive input
- The polarity input on procedures has changed name to differentiate it from ClkActive. Expected impact is minimal. Named association calls will need to be updated with the new name. Procedures impacted: WaitForTransaction, WaitForTransactionOrIrq, WaitForBarrier(2), WaitForClock, WaitForLevel
- Moved CreateClock and CreateReset and friends from TbUtilPkg to ClockResetPkg
- CoveragePkg: Coverage models with Coverage Weight of 0 print last and are hidden in the html by default
- MemoryGenericPkg
- Throws Errors on AddrWidth > 40 and warnings if AddrWidth > 36.
- With the Error message, AddrWidth is truncated to 40 and the memory tries to operate.
- Note some simulators die even at AddrWidth = 36.
- Thanks to those reported tool crashes without warnings.
- ClockResetPkg
- Updated CreateClock with Offset, ClkActive, and Enable . Clock starts with ClkActive value after the Offset. At startup it has the initial signal value if set, otherwise, not ClkActive (if Offset > 0 sec).
- Old version of create clock is available as OldCreateClock. Its startup behavior is slightly different.
- Old version of create clock is available as CreateClock when ClockResetVersion is set to 2024.05 or less in OsvvmSettingsLocal.tcl. New versions will not be available though.
- Added CreateJitterClock whose jitter is controlled by a coverage model
- Thanks to those who continued asking about an upgrade to CreateClock
- ScoreboardPkg
- Made all generic functions impure
- Added scoreboards for unsigned, signed, and integer_vector (IntV)
- ReportPkg
- Added TimeOut input to EndOfTestReports
- Added scoreboard reporting for: unsigned, signed, and integer_vector (IntV)
- Scripts
- Include now has better error handling and restoration of state
- Updated support for Synopsys VCS, Cadence Xcelium, and added support for Siemens Visualizer
- Fixed DoWaves for Aldec. Fixed SetLogEnable.
- AXI4
- Shortened AlertLogID Names to improve reports
- AxiStreamReceiver - Added OsvvmVcInit to support setting of WaitForGet before TReady is active.
- UART: Minor updates to work around tool issues (Synopsys VCS and Cadence Xcelium).
- Regressions run on
- GHDL 4.1.0. Latest release run on GitHub Actions
- NVC 1.13.0
- Aldec RivieraPRO 2023.10
- Aldec ActiveHDL 14
- Aldec VSimSA 14 (related to ActiveHDL)
- Siemens Questa 2024.02_1.
- Siemens Visualizer 2024.02_1 runs and individual tests pass, but hangs when running a large number of test cases
- Synopsys VCS V-2023.12-SP2
- Cadence Xcelium 2024.03 - passes osvvm library internal tests, but does not pass the OSVVM public tests (for OSVVM VC)
- Xilinx XSIM 2024.1 - passes osvvm library internal tests, but does not pass the OSVVM public tests (for OSVVM VC)
To download the release as a zip, see: https://osvvm.org/downloads