Skip to content

feat: Include private HUGR functions in the local symbol table #2831

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
cgh-qtnm merged 3 commits into from
Mar 11, 2026
Merged

feat: Include private HUGR functions in the local symbol table #2831

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
1eb65cd
s/Private/Internal
cgh-qtnm Jan 9, 2026
713c133
Merge branch 'main' into george/internal-linkage...
cgh-qtnm Mar 10, 2026
fb4e3b1
Merge branch 'main' into george/internal-linkage
cgh-qtnm Mar 11, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion hugr-llvm/src/emit.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -139,7 +139,7 @@ impl<'c, 'a, H> EmitModuleContext<'c, 'a, H> {
let name = self.name_func(name, node);
match visibility {
Visibility::Public => self.get_func_impl(name, llvm_func_ty, Some(Linkage::External)),
Visibility::Private => self.get_func_impl(name, llvm_func_ty, Some(Linkage::Private)),
Visibility::Private => self.get_func_impl(name, llvm_func_ty, Some(Linkage::Internal)),
_ => self.get_func_impl(name, llvm_func_ty, None),
}
}
Expand Down
2 changes: 1 addition & 1 deletion ...-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private i8 @_hl.main.1(i8 %0, i8 %1) {
define internal i8 @_hl.main.1(i8 %0, i8 %1) {
alloca_block:
br label %entry_block

Expand Down
91 changes: 91 additions & 0 deletions ...it/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@pre-mem2reg@llvm14.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,91 @@
---
source: hugr-llvm/src/emit/ops/cfg.rs
expression: mod_str
---
; ModuleID = 'test_context'
source_filename = "test_context"

define internal i8 @_hl.main.1(i8 %0, i8 %1) {
alloca_block:
%"0" = alloca i8, align 1
%"2_0" = alloca i8, align 1
%"2_1" = alloca i8, align 1
%"4_0" = alloca i8, align 1
%"7_0" = alloca i8, align 1
%"7_1" = alloca i8, align 1
%"03" = alloca i8, align 1
%"11_0" = alloca i8, align 1
%"11_1" = alloca i8, align 1
%"9_0" = alloca { i8, i8 }, align 8
%"13_0" = alloca { i1, i8 }, align 8
br label %entry_block

entry_block: ; preds = %alloca_block
store i8 %0, i8* %"2_0", align 1
store i8 %1, i8* %"2_1", align 1
%"2_01" = load i8, i8* %"2_0", align 1
%"2_12" = load i8, i8* %"2_1", align 1
store i8 %"2_01", i8* %"7_0", align 1
store i8 %"2_12", i8* %"7_1", align 1
br label %2

2: ; preds = %11, %entry_block
%"7_04" = load i8, i8* %"7_0", align 1
%"7_15" = load i8, i8* %"7_1", align 1
store i8 %"7_04", i8* %"7_0", align 1
store i8 %"7_15", i8* %"7_1", align 1
%"7_06" = load i8, i8* %"7_0", align 1
%"7_17" = load i8, i8* %"7_1", align 1
%3 = insertvalue { i8, i8 } poison, i8 %"7_06", 0
%4 = insertvalue { i8, i8 } %3, i8 %"7_17", 1
store { i8, i8 } %4, { i8, i8 }* %"9_0", align 1
%"9_08" = load { i8, i8 }, { i8, i8 }* %"9_0", align 1
store { i8, i8 } %"9_08", { i8, i8 }* %"9_0", align 1
%"9_09" = load { i8, i8 }, { i8, i8 }* %"9_0", align 1
switch i1 false, label %5 [
]

5: ; preds = %2
%6 = extractvalue { i8, i8 } %"9_09", 0
%7 = extractvalue { i8, i8 } %"9_09", 1
store i8 %6, i8* %"11_0", align 1
store i8 %7, i8* %"11_1", align 1
br label %8

8: ; preds = %5
%"11_011" = load i8, i8* %"11_0", align 1
%"11_112" = load i8, i8* %"11_1", align 1
store i8 %"11_011", i8* %"11_0", align 1
store i8 %"11_112", i8* %"11_1", align 1
%"11_013" = load i8, i8* %"11_0", align 1
%9 = insertvalue { i1, i8 } { i1 false, i8 poison }, i8 %"11_013", 1
store { i1, i8 } %9, { i1, i8 }* %"13_0", align 1
%"13_014" = load { i1, i8 }, { i1, i8 }* %"13_0", align 1
%"11_115" = load i8, i8* %"11_1", align 1
store { i1, i8 } %"13_014", { i1, i8 }* %"13_0", align 1
store i8 %"11_115", i8* %"11_1", align 1
%"13_016" = load { i1, i8 }, { i1, i8 }* %"13_0", align 1
%"11_117" = load i8, i8* %"11_1", align 1
%10 = extractvalue { i1, i8 } %"13_016", 0
switch i1 %10, label %11 [
i1 true, label %13
]

11: ; preds = %8
%12 = extractvalue { i1, i8 } %"13_016", 1
store i8 %12, i8* %"7_0", align 1
store i8 %"11_117", i8* %"7_1", align 1
br label %2

13: ; preds = %8
store i8 %"11_117", i8* %"03", align 1
br label %14

14: ; preds = %13
%"010" = load i8, i8* %"03", align 1
store i8 %"010", i8* %"4_0", align 1
%"4_018" = load i8, i8* %"4_0", align 1
store i8 %"4_018", i8* %"0", align 1
%"019" = load i8, i8* %"0", align 1
ret i8 %"019"
}
2 changes: 1 addition & 1 deletion ...it/ops/snapshots/hugr_llvm__emit__ops__cfg__test__diverse_outputs@pre-mem2reg@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private i8 @_hl.main.1(i8 %0, i8 %1) {
define internal i8 @_hl.main.1(i8 %0, i8 %1) {
alloca_block:
%"0" = alloca i8, align 1
%"2_0" = alloca i8, align 1
Expand Down
2 changes: 1 addition & 1 deletion hugr-llvm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private i1 @_hl.main.1(i2 %0, i1 %1) {
define internal i1 @_hl.main.1(i2 %0, i1 %1) {
alloca_block:
br label %entry_block

Expand Down
158 changes: 158 additions & 0 deletions ...vm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@pre-mem2reg@llvm14.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,158 @@
---
source: hugr-llvm/src/emit/ops/cfg.rs
expression: mod_str
---
; ModuleID = 'test_context'
source_filename = "test_context"

define internal i1 @_hl.main.1(i2 %0, i1 %1) {
alloca_block:
%"0" = alloca i1, align 1
%"5_0" = alloca {}, align 8
%"2_0" = alloca i2, align 1
%"2_1" = alloca i1, align 1
%"6_0" = alloca i1, align 1
%"9_0" = alloca i2, align 1
%"9_1" = alloca i1, align 1
%"03" = alloca i1, align 1
%"11_0" = alloca i1, align 1
%"06" = alloca i1, align 1
%"20_0" = alloca i1, align 1
%"25_0" = alloca i1, align 1
%"39_0" = alloca i1, align 1
%"44_0" = alloca i1, align 1
br label %entry_block

entry_block: ; preds = %alloca_block
store {} undef, {}* %"5_0", align 1
store i2 %0, i2* %"2_0", align 1
store i1 %1, i1* %"2_1", align 1
%"2_01" = load i2, i2* %"2_0", align 1
%"2_12" = load i1, i1* %"2_1", align 1
store i2 %"2_01", i2* %"9_0", align 1
store i1 %"2_12", i1* %"9_1", align 1
br label %2

2: ; preds = %entry_block
%"9_04" = load i2, i2* %"9_0", align 1
%"9_15" = load i1, i1* %"9_1", align 1
store i2 %"9_04", i2* %"9_0", align 1
store i1 %"9_15", i1* %"9_1", align 1
br label %8

3: ; preds = %19
store i1 true, i1* %"39_0", align 1
%"5_025" = load {}, {}* %"5_0", align 1
%"39_026" = load i1, i1* %"39_0", align 1
store {} %"5_025", {}* %"5_0", align 1
store i1 %"39_026", i1* %"39_0", align 1
%"5_027" = load {}, {}* %"5_0", align 1
%"39_028" = load i1, i1* %"39_0", align 1
switch i1 false, label %4 [
]

4: ; preds = %3
store i1 %"39_028", i1* %"03", align 1
br label %7

5: ; preds = %20
store i1 false, i1* %"44_0", align 1
%"5_029" = load {}, {}* %"5_0", align 1
%"44_030" = load i1, i1* %"44_0", align 1
store {} %"5_029", {}* %"5_0", align 1
store i1 %"44_030", i1* %"44_0", align 1
%"5_031" = load {}, {}* %"5_0", align 1
%"44_032" = load i1, i1* %"44_0", align 1
switch i1 false, label %6 [
]

6: ; preds = %5
store i1 %"44_032", i1* %"03", align 1
br label %7

7: ; preds = %6, %4
%"024" = load i1, i1* %"03", align 1
store i1 %"024", i1* %"6_0", align 1
%"6_033" = load i1, i1* %"6_0", align 1
store i1 %"6_033", i1* %"0", align 1
%"034" = load i1, i1* %"0", align 1
ret i1 %"034"

8: ; preds = %2
%"9_07" = load i2, i2* %"9_0", align 1
store i2 %"9_07", i2* %"9_0", align 1
%"9_08" = load i2, i2* %"9_0", align 1
switch i2 %"9_08", label %9 [
i2 1, label %10
i2 -2, label %11
]

9: ; preds = %8
br label %12

10: ; preds = %8
br label %14

11: ; preds = %8
br label %16

12: ; preds = %9
store i1 true, i1* %"20_0", align 1
%"5_010" = load {}, {}* %"5_0", align 1
%"20_011" = load i1, i1* %"20_0", align 1
store {} %"5_010", {}* %"5_0", align 1
store i1 %"20_011", i1* %"20_0", align 1
%"5_012" = load {}, {}* %"5_0", align 1
%"20_013" = load i1, i1* %"20_0", align 1
switch i1 false, label %13 [
]

13: ; preds = %12
store i1 %"20_013", i1* %"06", align 1
br label %18

14: ; preds = %10
store i1 false, i1* %"25_0", align 1
%"5_014" = load {}, {}* %"5_0", align 1
%"25_015" = load i1, i1* %"25_0", align 1
store {} %"5_014", {}* %"5_0", align 1
store i1 %"25_015", i1* %"25_0", align 1
%"5_016" = load {}, {}* %"5_0", align 1
%"25_017" = load i1, i1* %"25_0", align 1
switch i1 false, label %15 [
]

15: ; preds = %14
store i1 %"25_017", i1* %"06", align 1
br label %18

16: ; preds = %11
%"5_018" = load {}, {}* %"5_0", align 1
%"9_119" = load i1, i1* %"9_1", align 1
store {} %"5_018", {}* %"5_0", align 1
store i1 %"9_119", i1* %"9_1", align 1
%"5_020" = load {}, {}* %"5_0", align 1
%"9_121" = load i1, i1* %"9_1", align 1
switch i1 false, label %17 [
]

17: ; preds = %16
store i1 %"9_121", i1* %"06", align 1
br label %18

18: ; preds = %17, %15, %13
%"09" = load i1, i1* %"06", align 1
store i1 %"09", i1* %"11_0", align 1
%"11_022" = load i1, i1* %"11_0", align 1
store i1 %"11_022", i1* %"11_0", align 1
%"11_023" = load i1, i1* %"11_0", align 1
switch i1 %"11_023", label %19 [
i1 true, label %20
]

19: ; preds = %18
br label %3

20: ; preds = %18
br label %5
}
2 changes: 1 addition & 1 deletion ...vm/src/emit/ops/snapshots/hugr_llvm__emit__ops__cfg__test__nested@pre-mem2reg@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private i1 @_hl.main.1(i2 %0, i1 %1) {
define internal i1 @_hl.main.1(i2 %0, i1 %1) {
alloca_block:
%"0" = alloca i1, align 1
%"5_0" = alloca {}, align 8
Expand Down
2 changes: 1 addition & 1 deletion ...llvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private i1 @_hl.main.1() {
define internal i1 @_hl.main.1() {
alloca_block:
br label %entry_block

Expand Down
2 changes: 1 addition & 1 deletion ...t/snapshots/hugr_llvm__emit__test__test_fns__diverse_cfg_children@pre-mem2reg@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private i1 @_hl.main.1() {
define internal i1 @_hl.main.1() {
alloca_block:
%"0" = alloca i1, align 1
%"4_0" = alloca i1, align 1
Expand Down
4 changes: 2 additions & 2 deletions ...m/src/emit/snapshots/hugr_llvm__emit__test__test_fns__diverse_module_children@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,15 +5,15 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private void @_hl.f1.1() {
define internal void @_hl.f1.1() {
alloca_block:
br label %entry_block

entry_block: ; preds = %alloca_block
ret void
}

define private void @_hl.f2.4() {
define internal void @_hl.f2.4() {
alloca_block:
br label %entry_block

Expand Down
4 changes: 2 additions & 2 deletions ...napshots/hugr_llvm__emit__test__test_fns__diverse_module_children@pre-mem2reg@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,15 +5,15 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private void @_hl.f1.1() {
define internal void @_hl.f1.1() {
alloca_block:
br label %entry_block

entry_block: ; preds = %alloca_block
ret void
}

define private void @_hl.f2.4() {
define internal void @_hl.f2.4() {
alloca_block:
br label %entry_block

Expand Down
2 changes: 1 addition & 1 deletion ...lvm/src/emit/snapshots/hugr_llvm__emit__test__test_fns__emit_hugr_conditional@llvm21.snap
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ expression: mod_str
; ModuleID = 'test_context'
source_filename = "test_context"

define private { { i2, i2, i1 }, {} } @_hl.main.1({ i2, i2, i1 } %0, {} %1) {
define internal { { i2, i2, i1 }, {} } @_hl.main.1({ i2, i2, i1 } %0, {} %1) {
alloca_block:
br label %entry_block

Expand Down
Loading
Loading