Add AMD Zen5 Granite Ridge (Ryzen 9000) support

[zayac]

Adds support for AMD Granite Ridge desktop CPUs (Ryzen 9000 series), family 0x1A model 0x44, exposed as a new ZEN5_RYZEN model constant.

Granite Ridge shares the Zen 5 core with EPYC (ZEN5_EPYC), so the existing Zen5 event tables are reused unchanged. ZEN5_RYZEN is added alongside ZEN5_EPYC/ZEN5C_EPYC in every relevant switch/conditional.

Tested on AMD Ryzen 9 9950X3D with CLOCK/L2CACHE/L3CACHE/MEM groups.

cat /proc/cpuinfo contains

cpu family      : 26
model           : 68
model name      : AMD Ryzen 9 9950X3D 16-Core Processor

[TomTheBear]

Thanks for the addition. Unfortunately, there is no public documentation for family 0x1A model 0x44 yet. So it is unclear whether the platform provides the exact same counters/events as the existing ZEN5_EPYC. I have to delay the merge until we can check that.

Since there was a recent fix regarding Zen5, can you please apply your patches to #745 (branch amd_zen45_df_count_fix) and test again. Also try likwid-perfctr -e as used in the linked issue.

[zayac]

Thanks for the feedback. Done and SGTM to wait.

likwid-perfctr -i | head -10

--------------------------------------------------------------------------------
CPU name:       AMD Ryzen 9 9950X3D 16-Core Processor          
CPU type:       AMD K1A (Zen5) architecture
CPU clock:      4.29 GHz
CPU family:     26
CPU model:      68
CPU vendor:     0
CPU part:       0
CPU short:      zen5
CPU stepping:   0

likwid-perfctr -e | sed -n '/^Counter tags/,/^Event tags/p' | head -n -2

Counter tags(name, type<, options>):
FIXC0, Fixed counters
FIXC1, Fixed counters
FIXC2, Fixed counters
PMC0, Core-local general purpose counters, EDGEDETECT|THRESHOLD|INVERT|KERNEL
PMC1, Core-local general purpose counters, EDGEDETECT|THRESHOLD|INVERT|KERNEL
PMC2, Core-local general purpose counters, EDGEDETECT|THRESHOLD|INVERT|KERNEL
PMC3, Core-local general purpose counters, EDGEDETECT|THRESHOLD|INVERT|KERNEL
PMC4, Core-local general purpose counters, EDGEDETECT|THRESHOLD|INVERT|KERNEL
PMC5, Core-local general purpose counters, EDGEDETECT|THRESHOLD|INVERT|KERNEL
CPMC0, L3 Cache, TID|CID|SLICE
CPMC1, L3 Cache, TID|CID|SLICE
CPMC2, L3 Cache, TID|CID|SLICE
CPMC3, L3 Cache, TID|CID|SLICE
CPMC4, L3 Cache, TID|CID|SLICE
CPMC5, L3 Cache, TID|CID|SLICE
PWR0, AMD RAPL
PWR1, AMD RAPL
DFC0, Data Fabric
DFC1, Data Fabric
DFC2, Data Fabric
DFC3, Data Fabric
DFC4, Data Fabric
DFC5, Data Fabric
DFC6, Data Fabric
DFC7, Data Fabric
DFC8, Data Fabric
DFC9, Data Fabric
DFC10, Data Fabric
DFC11, Data Fabric
DFC12, Data Fabric
DFC13, Data Fabric
DFC14, Data Fabric
DFC15, Data Fabric
UMC0C0, Unified Memory Controller, MASK0
UMC0C1, Unified Memory Controller, MASK0
UMC0C2, Unified Memory Controller, MASK0
UMC0C3, Unified Memory Controller, MASK0
UMC1C0, Unified Memory Controller, MASK0
UMC1C1, Unified Memory Controller, MASK0
UMC1C2, Unified Memory Controller, MASK0
UMC1C3, Unified Memory Controller, MASK0

likwid-perfctr -f -C 0 -g FLOPS_DP ./bench/likwid-bench -t copy -w S0:1GB:1

--------------------------------------------------------------------------------
CPU name:       AMD Ryzen 9 9950X3D 16-Core Processor          
CPU type:       AMD K1A (Zen5) architecture
CPU clock:      4.29 GHz
--------------------------------------------------------------------------------
Allocate: Process running on hwthread 0 (Domain S0) - Vector length 62500000/500000000 Offset 0 Alignment 512
Allocate: Process running on hwthread 0 (Domain S0) - Vector length 62500000/500000000 Offset 0 Alignment 512
--------------------------------------------------------------------------------
LIKWID MICRO BENCHMARK
Test: copy
--------------------------------------------------------------------------------
Using 1 work groups
Using 1 threads
--------------------------------------------------------------------------------
Running without Marker API. Activate Marker API with -m on commandline.
--------------------------------------------------------------------------------
Group: 0 Thread 0 Global Thread 0 running on hwthread 0 - Vector length 62500000 Offset 0
--------------------------------------------------------------------------------
Cycles:                 7090984832
CPU Clock:              4291941745
Cycle Clock:            4291941745
Time:                   1.652162e+00 sec
Iterations:             64
Iterations per thread:  64
Inner loop executions:  15625000
Size (Byte):            1000000000
Size per thread:        1000000000
Number of Flops:        0
MFlops/s:               0.00
Data volume (Byte):     64000000000
MByte/s:                38737.11
Cycles per update:      1.772746
Cycles per cacheline:   14.181970
Loads per update:       1
Stores per update:      1
Load bytes per element: 8
Store bytes per elem.:  8
Load/store ratio:       1.00
Instructions:           11000000016
UOPs:                   14000000000
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Group 1: FLOPS_DP
+-------------------------------------+---------+-------------+
|                Event                | Counter |  HWThread 0 |
+-------------------------------------+---------+-------------+
|           ACTUAL_CPU_CLOCK          |  FIXC1  | 26717377496 |
|            MAX_CPU_CLOCK            |  FIXC2  | 21508102189 |
|         RETIRED_INSTRUCTIONS        |   PMC0  | 32010798621 |
|         CPU_CLOCKS_UNHALTED         |   PMC1  | 25673993309 |
|                MERGE                |   PMC3  |           0 |
| RETIRED_SSE_AVX_FLOPS_ALL_DP_SCALAR |   PMC2  |          67 |
|                MERGE                |   PMC5  |           0 |
| RETIRED_SSE_AVX_FLOPS_ALL_DP_PACKED |   PMC4  |           0 |
+-------------------------------------+---------+-------------+

+----------------------+--------------+
|        Metric        |  HWThread 0  |
+----------------------+--------------+
|  Runtime (RDTSC) [s] |       6.2050 |
| Runtime unhalted [s] |       6.2251 |
|      Clock [MHz]     |    5331.4153 |
|          CPI         |       0.8020 |
|     DP [MFLOP/s]     | 1.079779e-05 |
+----------------------+--------------+

[TomTheBear]

Can you please run the code provided by @loonatick-src in #744 (comment) . It looks strange to me that the system has only 2 memory controllers UMC[0,1] but 16 DFC counters. Not all Zen variants provide the number of DataFabric counters (NumPerfCtrNB) via CPUID.

[zayac]

Here is the output of the probe from #744.

CPUID leaf 0x80000022 (AMD Performance Monitoring and Debug)
  EAX = 0x00000007
  EBX = 0x00084106
  ECX = 0x00000003
  EDX = 0x00000000

EAX breakdown:
  PerfMonV2 supported : yes
EBX breakdown:
  Core PMC count      : 6
  DF (NB) PMC count   : 16
  UMC PMC count       : 8
ECX breakdown:
  Active UMC mask     : 0x00000003
  Active UMC count    : 2
  PMCs per UMC        : 4

So there are genuinely 16 DFC counters exposed, matching the ZEN5_EPYC count. I also validated FLOPS_DP, DATA, MEM, and L3CACHE against likwid benchmark. They report sensible numbers.

[TomTheBear]

I just checked AMD's documentation page and unfortunately, still no docs for this variant.