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Shivaaaydv/README.md

🌟 Hi, I'm Shiva Yadav

🛠️ Electronics Engineering | VLSI | RTL Design | FPGA Systems

🧑‍💻 About Me

🔹 Final-year Electronics Engineering student specializing in VLSI, RTL Design, and Digital Electronics
🔹 Skilled in Verilog/SystemVerilog, FPGA development, and ASIC flows
🔹 Experience with OpenLane, Yosys, OpenROAD and digital system verification
🔹 Built RTL designs like ALUs, FSMs, sequential circuits
🔹 Completed internships at SVNIT Surat & IGTR Ahmedabad

💼 Internship Experience

🏛️ SVNIT Surat — VLSI Physical Design Intern (June–July 2025)

➡️ Worked on RTL → GDSII using OpenLane: synthesis, floorplan, placement, routing, timing.

🏭 IGTR Ahmedabad — VLSI Design Intern (Jan–Feb 2025)

➡️ Designed CMOS circuits using Microwind & DSCH, understanding layout and logic behavior.

🛠️ Skills

🔧 Core

Digital Electronics • CMOS Logic • RTL Design • Timing Analysis • Sequential Circuits

💻 HDL Languages

Verilog SystemVerilog UVM VHDL

🧰 EDA Tools

ModelSim Icarus Verilog GTKWave Vivado Yosys OpenLane OpenROAD Microwind DSCH

🧑‍💻 Programming

C C++ Python

🐧 Other

Linux STA Basics Testbench Writing

🚀 Projects

📘 4-bit ALU Design — Verilog + testbench + synthesis
🚦 Traffic Light Controller (FSM) — fully verified state machine
🔄 Flip-Flop & Sequential Circuits Library — D, T, JK, SR with waveform verification

📌 Pinned Work

📍 4-bit ALU (Verilog)
📍 Traffic Light Controller FSM
📍 Sequential Circuit Library
📍 OpenLane RTL → GDSII Flow

🔗 Connect

🌐 LinkedIn: shivaa-yadav
💻 GitHub: Shivaaaydv
📧 Email: [email protected]

🎯 Current Focus

  • Improving skills in SystemVerilog, UVM, and verification methods
  • Learning FPGA-based SoC design and soft-core processor integration
  • Implementing and verifying UART, SPI, I2C
  • Learning AMBA (APB, AHB, AXI) on-chip protocols
  • Exploring ASIC Physical Design using OpenLane
  • Building stronger RTL + Verification projects
  • Working on FPGA-based Image Processing

📘 About This Profile

A collection of my work in VLSI Design, RTL Engineering, Verification, Digital Logic, and FPGA systems, built through hands-on projects and industry internships.

Popular repositories Loading

  1. VLSI-CODES VLSI-CODES Public

    This repository contains a collection of VLSI design projects implemented using Verilog HDL. All designs are simulated and verified using EDA Playground or Xilinx Vivado.

  2. I2C- I2C- Public

  3. AND-Gate AND-Gate Public

    SystemVerilog

  4. Shivaaaydv Shivaaaydv Public

    GitHub portfolio showcasing my work in RTL design, FPGA prototyping, Verilog/SystemVerilog projects, and VLSI design internships.

  5. Traffic-light-controller Traffic-light-controller Public

    Verilog Traffic Light Controller (FSM) + testbench + waveform

    Verilog

  6. 4bit-alu 4bit-alu Public

    A fully synthesizable 4-bit Arithmetic Logic Unit (ALU) implemented in Verilog, including a clean testbench, waveform outputs, and documentation. Designed for FPGA/RTL learning, academic projects, …

    Verilog