[pull] master from verilog-to-routing:master #565
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libarchfpga
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[Pack] Removed Unused Log Messages
…tile (#3320) * [test] add new test case to validate direct connection from two identify source subtile to single destination subtile * [core] now to_port name is also checked in building direction connection * [core] typo * [test] debug * [test] update golden * [core] code comments format
…wires Add interposer wires
Make t_rr_graph_storage::sort_edge compatible with C++17
…_convention Make read_xml_arch_file more compliant with doing style
Generalize Parmys Mult_Split to Allow for Multipliers Whose Input Widths are not Equal
Bumps [libs/EXTERNAL/libcatch2](https://github.com/catchorg/Catch2) from `b3fb4b9` to `31ee3be`. - [Release notes](https://github.com/catchorg/Catch2/releases) - [Commits](catchorg/Catch2@b3fb4b9...31ee3be) --- updated-dependencies: - dependency-name: libs/EXTERNAL/libcatch2 dependency-version: 31ee3beb0a474463e0101674c22f2fef0311d601 dependency-type: direct:production ... Signed-off-by: dependabot[bot] <[email protected]>
…s/libs/EXTERNAL/libcatch2-31ee3be Bump libs/EXTERNAL/libcatch2 from `b3fb4b9` to `31ee3be`
The code for reading a netlist file was very hard to follow and made it challenging to try and improve the pb interface. Went through and cleaned up the code to make it a bit more obvious what it is trying to do.
…eanup [Pack] Cleaned Up Read Netlist Code
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