tests: remove unstable FPGA synthesis result checks

Author: widlarizer

tests/arch/quicklogic/pp3/fsm.ys

@@ -11,8 +11,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd fsm # Constrain all select calls below inside the top module
 
-select -assert-count 2 t:LUT2
-select -assert-count 4 t:LUT3
 select -assert-count 4 t:dffepc
 select -assert-count 1 t:logic_0
 select -assert-count 1 t:logic_1

tests/arch/xilinx/dsp_cascade.ys

@@ -69,7 +69,8 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
 design -load postopt
 cd cascade
 select -assert-count 2 t:DSP48E1
-select -assert-none t:DSP48E1 t:BUFG %% t:* %D
+# TODO Disabled check, FDREs emitted due to order sensitivity
+# select -assert-none t:DSP48E1 t:BUFG %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)
 select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i