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Signed comparison with nested ternary subtraction is mis-synthesized
pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproductionStatus: Open.#6063 In YosysHQ/yosys;synth_xilinxDSP packing asserts (crashes) on a non-zero-init input registerpending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproductionStatus: Open.#6046 In YosysHQ/yosys;opt_dff -sat significantly slower for certain design patterns
pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproductionStatus: Open.#6016 In YosysHQ/yosys;- Status: Open.#6015 In YosysHQ/yosys;
Multi-bit unsized constant used in pass invocation triggers segfault instead of error
pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproductionStatus: Open.#6009 In YosysHQ/yosys;- Status: Open.#6002 In YosysHQ/yosys;
- Status: Open.#5998 In YosysHQ/yosys;
build error when
pyosysis enabled on Ubuntu 26.04 (dependency conflict)pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproductionStatus: Open.#5974 In YosysHQ/yosys;- Status: Open.#5957 In YosysHQ/yosys;
Wildcard package imports (
import pkg::*) fail to resolve typedefsSystemVerilogIssues and questions related to SystemVerilogIssues and questions related to SystemVerilogStatus: Open.#5947 In YosysHQ/yosys;techmap: incorrect lowering of unsigned $mod via $__div_mod_u produces wrong simulation result
pending-verificationThis issue is pending verification and/or reproductionThis issue is pending verification and/or reproductionStatus: Open.#5940 In YosysHQ/yosys;- Status: Open.#5917 In YosysHQ/yosys;