autoname: Fix selection arg

Author: KrystalDelusion

passes/cmds/autoname.cc

@@ -127,6 +127,7 @@ struct AutonamePass : public Pass {
 			// }
 			break;
 		}
+		extra_args(args, argidx, design);
 
 		log_header(design, "Executing AUTONAME pass.\n");
 

tests/various/autoname.ys

@@ -171,17 +171,20 @@ module \top
   end
 end
 EOT
-# wires all named for being cell outputs
+# wires are named for being cell outputs
 logger -expect log "Rename wire .d in top to or_Y" 1
+logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
+debug autoname t:$or
+logger -check-expected
+
 # $name gets shortest name (otherwise bcd_$__unknown_B)
 logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
-logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
 # another output wire
 logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
 # $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
 logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
 # $c gets shortest name, since the cell driving it doesn't have known port
 # directions
 logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
-debug autoname t:$and
+debug autoname
 logger -check-expected